Live Webinar: Enhance Your Productivity with Schematic Driven Layout
Date/Time: December 16, 2014 11:00 am PST / 2:00 pm EST
Learn about Tanner EDA’s Schematic Driven Layout and assisted routing. This webinar will include a tool demonstration on how to create layout that matches the schematic the first time. We will demonstrate how Tanner EDA’s SDL and assisted routing reduces manual routing in layout with automated instance, real-time net flylines, nets & pins tracking, geometry marking/highlighting/by net, ECO tracking and eliminating manual routing processes that can lead to LVS errors. Improve your layout by attending this educational tool demonstration.
Learn More About our Latest Product Release: HiPer Silicon Design Suite
Tanner EDA has released version 16.2 of HiPer Silicon Design Suite, including an all-new digital place and route tool, assisted routing in SDL, netlisting export directly to SDL, dynamic flylines, auto-tagging of net routes, IPL callback support, synchronized selection in S-Edit and L-Edit.
Tanner EDA partners with leading foundries to provide all-inclusive solutions for advanced process technologies. Our featured partner is:
Like learn more about Tanner EDA foundry relationships.
Featured Case Study
Tanner EDA Helps Customer and ASIC design house, Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance by using the mixed-signal design suite from Tanner EDA. View Case Study
Tanner EDA provides a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs). Learn more.
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Analog layout and Tanner's L-Edit and Specialty Tools
Analog acceleration and Tanner's HiPer DevGen tool
High performance physical verification and Tanner's HiPer Verify
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