Live Webinar: Adding a Digital Block to an Analog Design
Date/Time: October 30, 2014 11:00 am PST/2:00 pm EST
This webinar will take you through the process of adding a digital block to an analog design, starting from RTL behavioral code and proceeding through synthesis, place & route and static timing analysis. We’ll be taking a design through our flow, step-by-step, and you will see first-hand the implementation process that you would go through to add a digital block to an existing analog design.
Live Webinar: Mixed-Signal Verification – Bringing the Best of Both Worlds Together
Date/Time: November 6, 2014 8:00 am PST/11:00 am EST
In this webinar - presented jointly by Aldec and Tanner EDA - we will talk about the integrated solution for verification of mixed-signal IC designs. Traditionally highly accurate SPICE based simulation is very popular for the verification of analog designs, but it is too slow to deal with digital part. Event-driven digital simulation can handle digital portion, but fails when dealing with the analog design. The Tanner/Aldec co-simulation interface bridges the gap between these issues and provides a reliable solution using any combination of Verilog-AMS, Verilog-A, Verilog and SPICE netlists.
Learn More About our Latest Product Release: HiPer Silicon Design Suite
Tanner EDA has released version 16.2 of HiPer Silicon Design Suite, including an all-new digital place and route tool, assisted routing in SDL, netlisting export directly to SDL, dynamic flylines, auto-tagging of net routes, IPL callback support, synchronized selection in S-Edit and L-Edit.
Tanner EDA partners with leading foundries to provide all-inclusive solutions for advanced process technologies. Our featured partner is:
Like learn more about Tanner EDA foundry relationships.
Featured Case Study
Tanner EDA Helps Customer and ASIC design house, Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance by using the mixed-signal design suite from Tanner EDA. View Case Study
Tanner EDA provides a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs). Learn more.
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Analog layout and Tanner's L-Edit and Specialty Tools
Analog acceleration and Tanner's HiPer DevGen tool
High performance physical verification and Tanner's HiPer Verify
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