Live Webinar: Shortcuts to Streamline IC Layout & Productivity
Date: Tuesday, January 27, 2015
Time: 11:00 am PST/2:00 pm EST
As the saying goes, time is money. When you are plunked down in front of your computer doing layout day in and day out, every unnecessary click you have to do takes away precious time to market. Fear not!!! Tanner EDA tool L-Edit is the solution to increase IC Layout productivity. Attend this webinar to learn about shortcuts and features to streamline your layout experience and eliminate cumbersome tasks that decrease productivity. Whether you are doing IC layout, MEMS, or any other types of layout, you can benefit from this webinar.
Learn More About our Latest Product Release: HiPer Silicon Design Suite
Tanner EDA has released version 16.2 of HiPer Silicon Design Suite, including an all-new digital place and route tool, assisted routing in SDL, netlisting export directly to SDL, dynamic flylines, auto-tagging of net routes, IPL callback support, synchronized selection in S-Edit and L-Edit.
Tanner EDA partners with leading foundries to provide all-inclusive solutions for advanced process technologies. Our featured partner is:
Like learn more about Tanner EDA foundry relationships.
Featured Case Study
Tanner EDA Helps Customer and ASIC design house, Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance by using the mixed-signal design suite from Tanner EDA. View Case Study
Tanner EDA provides a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs). Learn more.
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Analog layout and Tanner's L-Edit and Specialty Tools
Analog acceleration and Tanner's HiPer DevGen tool
High performance physical verification and Tanner's HiPer Verify
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