Is a New Paradigm for Nanoscale Analog CMOS Design Needed?
Copyright © 2011 IEEE. Reprinted from Proceedings of the IEEE | Vol. 99, No. 1, January 2011.
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I. AN OLD “NEW PARADIGM” FOR DIGITAL DESIGN
As the electronic design automation (EDA) industry strives to keep pace with new complementary metal–oxide–semiconductor (CMOS) process technology, analog postlayout verification tools are identifying a wider range of circuit and physical design deficiencies. While the EDA tools have shown considerable progress, problems found during postlayout verification result in redesign and relayout time. Pretapeout verification and debug procedures used to take two weeks, but now may take more than two months. The required redesign wastes the semiconductor industries most valuable commodity, time to market.
One of several problems which must be overcome with each advance in nanoscale technology node is a widening difference (gap) between analog circuit pre- and postlayout simulation results. It is not unusual to find a 20% simulation gap for wideband analog circuits at 45 nm, with the gap increasing at the 32- and 22-nm nodes. Circuit redesign and relayout to increase analog bandwidth by 20% is often not a trivial task.
Poor lithographic pattern fidelity, mechanical stress effects, wiring parasitics, process variability, and many other physical effects further decrease the probability that a 45-nm analog CMOS circuit will perform with adequate margins. Leading integrated circuit (IC) design firms are therefore requiring circuit design engineers to also perform, or become more closely involved in the analog physical design at, and beyond, 45 nm.
Unfortunately, the participation of circuit design engineers in layout is becoming more difficult as the number of nanoscale design rules has gone up almost an order of magnitude in deep nanoscale technology nodes. The compute time for design-rule checks has also increased significantly at 22 nm as a result of the increase in 2-D rule-check operations (see Fig. 1).
Fig. 1. The number of design rules is increasing rapidly at the 45-nm node and beyond. At the 22-nm node, the typical number of rules has increased to approximately 2000. Image credit: David Abercrombie Mentor Graphics.
The work of Mead and Conway led to the development of a simple set of layout rules which enabled graduate students and engineers to perform, and later automate, digital IC physical design. It was based on a dimensionless parameter, LAMBDA, which was equal to one half minimum feature size (F) . The F/2 granularity contributed to layout area inefficiency; however, the resulting drawn and computer-generated physical designs could easily be ported to various technologies using the multiple-project MOSIS fabrication methodology that was transferred from Xerox PARC to USC. The Mead–Conway methodology enabled graduate students and engineers at Stanford and Xerox PARC in the 1980s to create the foundation SOC IC technology for SUN, SGI, Apollo, and MIPS.
In order to increase deep nanoscale analog physical design productivity and achieve acceptable layout area efficiency, a new design paradigm is proposed. The new paradigm includes using a set of restrictive physical design rules based on dimensionless GAMMA (Γ) layout units with a granularity of F/4. Circuit design productivity may be increased though the use of a dimensionless schematic notation is also based on F/4 units. The schematic notation proposed may be used in combination with a technology-specific file to enable rapid circuit simulation in a multitude of nanoscale technology nodes and platform options.
To support the new circuit and physical layout paradigm, it is necessary to utilize an EDA tool that will convert the GAMMA database to the target technology scale while preserving the cell hierarchy. A simple set of algorithms is proposed which will enable a layout tool to also hierarchically shrink and export the GAMMA data to GDSII data in micrometers. Existing tools which simply flatten and shrink the layout data create large file sizes. These sizes are much too large for time-efficient transport to the many tools used for nanoscale physical design verification.
II. NARROWING THE PRELAYOUT SIMULATION GAP
In prelayout simulation at the 45-nm node and beyond, device-model effective W, L, Vt, and gm in simulation can be modified by including several layout geometry-dependent factors. Prior to the nanoscale era of technology, only entry of device junction areas and some interconnect parasitics was required. At the 100-nm technology node, the distance to well edge was required to modify device Vt and compensate for the well proximity effect (WPE). Distance from gate to shallow trench isolation (STI) edge, SA and SB in Fig. 2, was introduced to modify both Vt and mobility to account for STI stress effects.
Fig. 2. An NMOS device layout pattern with fixed SA-SB distances. Minimizing distance from gate to cell ties (shown in green) is of critical importance in realizing the full gain-bandwidth potential of the device.
At 45-nm and beyond, stress and lithographic patterning effects have been added to modify device model parameters. These include X and Y distances to unrelated oxide definition areas and to gate poly patterns beyond the device cell. If the default values for these parameters cannot achieve accurate simulation results, then actual values must be entered. The prospects for automated parameter entry are not good as analog CMOS layout patterns are often symmetrical, but quite random. Unless a methodology is devised to mitigate the parameter entry problem, the gap between pre- and postlayout simulation accuracy is bound to increase with each new technology node.
One way to narrow the prelayout simulation accuracy gap is to restrict the CMOS device shape in a manner that will standardize, and therefore predetermine, many additional stress and lithography-related distance parameters. The new paradigm for analog CMOS device design includes restricting the number of gate fingers to two for a single device (see Fig. 2).
Minimizing the resistance through the substrate from the device gates to the substrate ties is of critical importance in realizing the full gain-bandwidth potential of the device. As this distance increases by locating the ties remotely, or adding additional gates, the high-frequency characteristics of the basic device are degraded. In simulation, this effect is observed as the resistance increases between the basic device model substrate node and the device-symbol substrate-voltage supply node.
III. INCREASING ANALOG IC MANUFACTURING YIELDS
As devices are scaled down, lithographic and stress effects are taking over from traditional analog IC manufacturing yield-limiting effects. While the EDA industry works to include more of these effects in circuit simulation, many are not yet modeled. Stress effects from overlying metal within a critical stress field of at least 2 µm are not included in present simulation models. As a result, manufacturability concerns are overtaking circuit density as the highest priorityin nanoscale IC physical design.
Fig. 3. Device cell ties are overlapped to create an amplifier physical design with area density uniformity and pattern regularity. Metal 1 gate interconnect length does not appreciably increase device gate capacitance.
Reticle enhancement techniques are used in nanoscale nodes to improve lithographic pattern fidelity. However, the resulting patterns no longer correspond on a 1 : 1 basis with the original layout. This creates mismatch in analog devices that must be identical in final dimensions. To preserve lithographic fidelity and increase yields in analog physical layout, restrictive design rules must be included in any new paradigm. For example, gate extensions must be longer and metal spacing must be wider than minimum. Analog layout area is not increased excessively by using gate extensions of 12Γ and increasing metal width and space from 6Γ in older technologies to 8Γ in nanoscale.
Many of the design-for- manufacturability (DFM) problems that are revealed in postlayout verification, and some that are not evident until after chip fabrication, may be mitigated by achieving pattern regularity and layer-by-layer area density uniformity. An important aspect of the new paradigm requires the device designer to choose device widths that create substantially uniform rows of devices. This practice does not impose unusual hardships on the circuit design as the requirement for a certain device gate length may be achieved by using multiple devices with the same gate width. A similar restriction is imposed on bipolar IC design where the designer must choose between a relatively small number of well modeled device geometries. A portion of an amplifier physical design is shown in Fig. 3. Device physical design has been modified from that of Fig. 2 to accommodate severe electromigration (EM) restrictions on the metal and intermetal-connection (VIA) current-carrying capabilities anticipated at the 22-nm technology node .
IV. INCREASING DESIGN PRODUCTIVITY
Physical layouts and circuit designs targeting specific technology platform variants (high-performance, low power, poly, or metal gate, etc.) are not easily ported to other platforms or nodes as a result of the increasingly fine granularity of the design rules. In order to increase circuit design productivity in porting to other platforms or nodes, a new paradigm for dimensionless schematic parameter notation can be used. Then, simple scripts may be used with a technology-specific file to scale the dimensionless data and export it to a netlist for simulation or layout versusschematic (LVS) comparison . It is then possible to design while running simulations in two or more technology variants.
W and L dimensions in the schematic can be based on multiples of unit drawn feature size F (see Fig. 4). If 1Γ =F/4, then a device with W = 32Γ and L = 6Γ is expressed as W/L = 8F/1F5,” where the text “F” may be considered to be a decimal point. In this example, 1F5 = 1.5F. A key feature of the F/4 GAMMA grid is granularity fine enough to both provide area efficiency and also enable a shrink to the typical deep-ultraviolet (UV) reticle grid spacing of 5 nm without requiring snap-to-grid operations that are unsuitable for analog.
Fig. 4. Cascode current source example with layout in Γ units on the right, and schematic in F units on the left. Because layout and schematic units are dimensionless, both may be ported to more than one technology node.
Some of the dimensionless layout rules can be adjusted to fit within the exact design rules of a target technology that is two or three nodes in the future. Adjustments are required because some dimensions, such as top metal and well spacing, do not scale. Layout databases are usually flattened when being scaled and resized to fit a new technology node. This allows the resize functions to be aware of all neighboring polygons which lie outside the cell boundary. However, a flattened layout database is much too big for large area nanoscale analog physical designs and results in excessive data transfer time.
A new algorithm is proposed to preserve cell hierarchy during resizing which consists of resizing each object individually through the hierarchy, then resizing a flattened version of the design database. Polygons on individual layers in the flattened database which overlap gap errors in the hierarchical database are then added back into the hierarchical database for the final resized design . The resulting corrected database is larger than the initial hierarchical database, but still orders of magnitude smaller than the resized flattened database.
V. SUMMARY AND CONCLUSION
Nanoscale analog CMOS IC design productivity is becoming a major concern for the semiconductor industry as chip device counts approach 1 billion at 32 nm and each technology offers a choice of several operating platform variants. A multitude of physical device pattern separation dimensions must now be entered into the prelayout simulation models in order to predict postlayout circuit performance accurately. The random nature of analog physical design, which focuses on signal flow and coupling, increases the randomness and difficulty of prelayout simulation parameter entry.
A new paradigm for analog circuit and physical design is presented which relies on restrictive design rules for device physical design. Additional rules restrict metal width and spacing, thereby replacing many foundry-specified 2-D design rules intended to mitigate lithographic problems from end and corner effects. The basic CMOS device shape is restricted in a manner that results in achieving pattern regularity and density uniformity when cell boundaries are overlapped. This aspect of pattern regularity is particularly important in narrowing the gap between pre- and postlayout simulation accuracy that is increasing at the 45-nm technology node and beyond.
In deep nanoscale CMOS design, there must be close collaboration between circuit and physical design activities in order to achieve pattern regularity and uniformity in the final layout. The collaboration must begin in the initial phases of design if long rework cycles following postlayout design verification are to be avoided. The methodology proposed prioritizes device performance and yields over area density and results in more than an order of magnitude reduction in total rule count at the 22-nmnode. Reducing rule count is an important incentive to allow the circuit designer to participate in the physical design process.
The new paradigm is not intended to replace traditional analog design and layout. But if prelayout simulation accuracy and shortening time to market are priorities, then it is important to simplify and increase the accuracy of prelayout model parameter entry. Area efficiency can be traded off against technology node portability, higher DFM yields, and physical design debugging and rework time to get an early jump into a new process technology node. ■