Tanner EDA Software Tools - Design Automation Conference (DAC) 2011
Visit us in our booth: 2231
The DAC Exhibit hall will be open from 9am â€“ 6pm each day Monday-Wednesday and weâ€™ll be featuring a wonderful mix of business partners and guest presenters throughout the three days.
We will be demonstrating a special pre-release version of our full-flow suite of tools â€“ HiPer Silicon v16.Â Building on Tannerâ€™s 23 year legacy of providing industry-leading price-performance and interoperability, this latest version includes full Open Access database compatibility for layout; enabling Designers to share files with colleagues and business partners using Si2 database standards.Â Larger design teams will appreciate the redesigned multi-user functionality that has been added along with our Open Access functionality.
In addition, attendees who view a demo of Tanner tools will be invited to return to our booth to enter a drawing for a chance to spin the Prize Wheel and win an Apple iPad, iPod, and other giveaways!Â Weâ€™ll be holding raffle drawings on Monday, Tuesday and Wednesday at 10:00 am, 1:00 pm and 4:00 pm. Youâ€™ve got to be present to win â€“ so stop by often and increase your chances of winning!
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*Images solely representations of types of prizes and do not reflect models and colors of actual prizes.
Read more about ourÂ Exhibitor ForumsÂ
Read more about ourÂ Technical PanelÂ Â
DAC Events At-a-Glance
Exhibitor Forums â€“ Monday, June 6, 2011
Location: Exhibitor Forum, Booth #1005
10:40 - 11:15am â€“ Analog IC Design â€“ Why a Cohesive Tool Flow Drives Productivity
Abstract:Â As Analog IC Designers strive to keep pace with the rapidly increasing market demands around quicker time-to-market, productivity has become a mandate. This presentation will discuss the productivity advantages afforded by using a cohesive analog design tool suite; comprised of schematic capture, simulation, layout, and physical verification. Â Findings from a recent survey of Analog IC Designers - touching on the key benefits and challenges they see with using a full-flow design suite â€“ will be presented and discussed.
Speakers: Mass Sivilotti â€“ Chief Scientist, Tanner EDA & John Zuk â€“ VP Marketing & Strategy, Tanner EDA (Both from Monrovia, California)
3:00 - 3:35pm â€“ Analog IC Design at the Edge: A New Twist for Nanoscale Productivity
Abstract:Â Nanoscale analog IC design productivity is a major concern as chip device counts approach 1 billion at 32 nm. A multitude of physical device pattern separation dimensions must now be entered into the prelayout simulation models to accurately predict postlayout circuit performance. Our approach - based on the seminal work of Mead and Conway - offers a novel method that enables rapid circuit simulation in a multitude of nanoscale technology nodes and platform options. The result is that prelayout simulation accuracy is improved; having a direct impact on increasing analog IC manufacturing yields while simultaneously increasing design productivity.
Speakers: Dr. Lanny Lewyn â€“ President, Lewyn Consulting â€“ Laguna Beach, California
Nicolas Williams â€“ Director of Product Management â€“ Tanner EDA, Monrovia, CaliforniaÂ
Booth Presentations â€“ Monday - Wednesday, June 6 - 8, 2011
Location: Booth #2231
1:00pm â€“ Monday, Tuesday, and Wednesday â€“ TowerJazz
Speaker: Ofer Tamir, Director CAD, Design Enablement & Support
Ofer Tamir has over 20 years of experience in EDA as a CAD engineer and manager.Â He worked for National Semiconductor in Israel from 1986 â€“ 1995 as a CAD engineer specializing in P&R design flow and physical verification and DSPG from 1995 â€“ 2001 before joining TowerJazz in 2001 where he was CAD layout groups manager.Â He has an M.A. in Mathematics & Computer Science.
10:00am â€“ Tuesdayâ€“ X-Fab
Speaker: Joerg Doblaski, Senior Engineer
Joerg Doblaski studied Electrical Engineering with a focus on information and communication technologies at the Technical University of Ilmenau, Germany.Â After graduation, he started his work at X-Fab as a design engineer and was responsible for test-chip design, simulation, and test preparation.Â Since 2007 he works on the development of PDKs for X-Fabâ€™s CMOS, BiCMOS and HV technologies and on the maintenance and improvement of X-Fabâ€™s mixed-signal design flow.
10:00am â€“ Wednesday â€“ Tanner EDA on HiPer Verify High Performance Physical Verification
Speaker: Jeff Miller, Director of Product Management
Jeff Miller is a Product Manager at Tanner EDA.Â He is responsible for Tannerâ€™s offerings in the areas of parasitic extraction, placement and routing automation, and Verilog-A simulation.Â As a Linux/Open Source expert and regular contributor, Jeff was a driving force in expanding Tanner EDAâ€™s tool suite to the Linux platform.Â Prior to joining Tanner, Jeff worked as a Design Engineer on numerous analog, digital, and mixed signal chip development projects for the defense, medical and commercial markets.Â Jeff is a graduate of Harvey Mudd College in Claremont, CA.
4:00pm â€“ Wednesdayâ€“ Tanner EDA on HiPer DevGen Layout Acceleration
Speaker: Nicolas Williams, Director of Product Management
Nicolas Williams, Tanner EDA director of product management, joined the company in 1997. Williams is responsible for specifying and leading product direction from concept to release for Tanner's EDA tools. His field of specialty is analog EDA and analog, mixed-signal, and RF IC design. Williams works closely with customers and development to determine emerging issues that can be addressed by EDA.Â Williams received his bachelors of science and masters of science degrees in electrical and computer engineering from the University of Tennessee. He has authored and edited articles about design issues for ECN and EE Times and is a member of IEEE.
Fifth Annual IPL Luncheon â€“ Monday, June 6, 2011
Location: San Diego Marriott, Marina Ballroom D-E
12:00 â€“ 1:30pm â€“ Interoperable PDK Standards are Here to Stay: New Era of Analog / Custom Innovation
IPL Alliance will present and update on the current and future success of IPL standards.Â Attendees will hear about:
- How the industry is embracing the IPL 1.0 standard
- Specs of the new interoperable design constraint standard
- Collaboration among standards: How oPDK and iPDK will work together
Location: Booth #3421
11:15am â€“ 12:00pm â€“ Why the Delay in Analog PDK?
Topic Area: Analog / Mixed-Signal / RF Design
Summary: Why does it take so long for foundries to release analog/mixed-signal process design kits (PDKs)? The amount of AMS content in your designs is growing, and the pressure to move to smaller process nodes is increasing. This is your chance to talk to the people who develop your PDKs and reference flows.
Speakers: Mass Sivilotti â€“ Tanner EDA, Monrovia, CA, Tom Quan â€“ Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA, and Ofer Tamir â€“ TowerJazz, Newport Beach, CA
Listen to Tom Quan talk about the Analog PDK panel that Tanner EDA is participating in on Wednesday morning June 8 at the DAC Pavilion.