Tanner EDAâ€™s HiPer Verifyâ„¢ is a comprehensive yet affordable solution for analog/mixed-signal IC design rule checking (DRC) and hierarchical netlist extraction. HiPer Verifyâ€™s verification engine is designed to take advantage of the hierarchy and repetition in todayâ€™s IC designs. HiPer Verifyâ€™s hierarchical rule checking engine finds violations in the cell where they occur. This enables you to correct a violation once rather than sorting through many duplicate violations as flat processing requires.
Most foundries provide DRC and LVS rules in CalibreÂ®, AssuraÂ®, or DraculaÂ® format. When you change your process or feature size, you must update your DRC and LVS rulesâ€”a time consuming process. With HiPer Verify, you can simply reference the new DRC or LVS command file from the foundry, meeting your existing standards right out of the box. You get the security of knowing you are running your rule files without modification or conversion, and the convenience of not having to perform translations.
You can increase your number of verification licenses without increasing your overall tool costs. With its native compatibility, you can integrate HiPer Verify into your existing tool flow with little effort. By limiting expensive tool licenses to only final verification, you will save money and reduce your maintenance costs.
- Integrates with L-Editâ„¢ layout editor for precise location of violations.
- Runs CalibreÂ®, AssuraÂ®, and DraculaÂ® foundry files natively, without conversion or modification.
- Performs background processing to allow you to fix violations while DRC is still running.
- Performs electrical rule checks (ERC) such as antenna checks.
- Highlights DRC errors in either the top cell or the cell where the violation occurred.
- Extract a hierarchical SPICE netlist from layout for LVS and post-layout simulation.
- Display short and open circuit warnings in the layout.
- Run batch DRC or netlist extraction on multiple cells.
- Zip through LVS with cross-probing from SPICE netlists and LVS results to layout or schematic and with enhanced navigation of SPICE netlists.