Slow DRC speeds using HiPerVerify on hierarchical layouts

by **bayview@ripnet.com** » Thu May 03, 2012 2:43 pm

Has anyone else found the DRC execution speed to be glacially slow on moderate size, yet very hierarchical layouts such as memories? A 40nm 512Kbit(approx) design with approximately 1500 rules takes HiPer Verify many hours (overnight), where Calibre runs in under a minute. What's worse is that if you double the size of the memory, the DRC time almost doubles. Doesn't sound very hierarchical to me. Has anyone found a way to better partition the hierarchy to speed up the checks (e.g. Use one-dimensional versus two-dimensional arrays? Use instances only and no arrays?)

by **maadi** » Sat May 26, 2012 1:14 am

Hi,

I am working with Tanner V 15.02 in 0.35 um CMOS technology. I got a problem in DRC and layout extraction. I followed the instructions but they were not completed. I wrote " netlistingForSimulation, avoidParDio" in “Calibre defines” part but I don't know what should I choose for "Extract Rules Sets to run" at the same window. In previous versions we were supposed to choose "XH035.ext" file but in newer versions it doesn't work furthermore. Can anybody guide me?

contact info:
maadi.mohammad@gmail.com