Difference between Aldec Riviera Pro and Riviera Pro TE
Difference between Aldec Riviera Pro and Riviera Pro TE
by Tanner_AE » Thu Nov 01, 2012 11:15 am
Difference between original Aldec Riviera Pro and Riviera Pro TE (Tanner Edition)
Re: Difference between Aldec Riviera Pro and Riviera Pro TE
by Tanner_AE » Thu Nov 01, 2012 11:17 am
Please refer to Aldec's web page for information regarding the capabilities in their version: http://www.aldec.com/en/products/functi ... figuration
Riviera PRO TE (Tanner Edition) contains the following capabilities.
Supported Standards
• VHDL IEEE 1076 (1987, 1993, 2002 and 2008)
• Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
• SystemVerilog IEEE 1800-2009 (Design)
Design Entry and Design Management
• HDL and Text Editor
• Auto-Complete and Code Templates
• Design Manager
• Customizable GUI Perspectives
• Macro, Tcl/TK, Perl script support
HDL Debug and Analysis
• Advanced Breakpoint Management
• Interactive Code Execution Tracing
• Waveform Viewer
• Post Simulation Debug
• Multiple Waveform Windows
Simulation/Verification
• Mixed Language
• Verilog Programming Language Interface (PLI/VPI)
• Incremental Compilation
• VHDL IEEE 1076™-2008 Encryption
• Verilog® IEEE 1364™-2005 Encryption
• 64-Bit Simulation
• Simulation Performance Optimization (Verilog/SystemVerilog, VHDL)
Riviera PRO TE (Tanner Edition) contains the following capabilities.
Supported Standards
• VHDL IEEE 1076 (1987, 1993, 2002 and 2008)
• Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
• SystemVerilog IEEE 1800-2009 (Design)
Design Entry and Design Management
• HDL and Text Editor
• Auto-Complete and Code Templates
• Design Manager
• Customizable GUI Perspectives
• Macro, Tcl/TK, Perl script support
HDL Debug and Analysis
• Advanced Breakpoint Management
• Interactive Code Execution Tracing
• Waveform Viewer
• Post Simulation Debug
• Multiple Waveform Windows
Simulation/Verification
• Mixed Language
• Verilog Programming Language Interface (PLI/VPI)
• Incremental Compilation
• VHDL IEEE 1076™-2008 Encryption
• Verilog® IEEE 1364™-2005 Encryption
• 64-Bit Simulation
• Simulation Performance Optimization (Verilog/SystemVerilog, VHDL)
nMZRGAhFeCVdPX
by Kalin » Tue Dec 25, 2012 3:33 am
Such a deep asewnr! GD&RVVF
Last bumped by Anonymous on Tue Dec 25, 2012 3:33 am.
- Kalin
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