Automation in nanoscale

[praire_ck]

Does analog CMOS layout methodology favor using automated layout methods when making the transition to deep nanoscale physical design?

[LannyL]

Significantly higher intermetal-dielectric capacitances and lower EM capabilities for both metal and VIA require a very high level of layout skill in interconnecting wideband analog components and circuits. The skill in crafting low parasitic capacitance (Cp) interconnect must merge well with new approaches to analog CMOS device layouts not commonly found in factory PDKs. These factors favor a return to a higher degree of custom, rather than automated, analog layout. In another example favoring analog custom layout, robotic dummy-layer fill is no longer a highly recommended analog layout strategy because of the combination of higher Cp and smaller density-check windows.