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Layout in nano scale

Layout in nano scale

Postby william_maccolloch » Thu Mar 08, 2012 3:21 pm

Does analog CMOS layout methodology have to change radically when making the transition to deep nanoscale physical design?
william_maccolloch
 

Re: Layout in nano scale

Postby LannyL » Thu Mar 08, 2012 3:22 pm

The changes accompanying the transitions at each technology node from 90nm to 28nm were incremental. However when comparing well designed 90nm to 28nm layouts, they often appear to be completely different. We are now in a physical design epoch where layout area efficiency has to take second priority over a highly crafted layout relying on pattern regularity, area density uniformity, unidirectional gates, and a multitude of other concerns in order to achieve IC manufacturability.
LannyL
 


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