Layout in nano scale

[william_Maccolloch]

Does analog CMOS layout methodology have to change radically when making the transition to deep nanoscale physical design?

[LannyL]

The changes accompanying the transitions at each technology node from 90nm to 28nm were incremental. However when comparing well designed 90nm to 28nm layouts, they often appear to be completely different. We are now in a physical design epoch where layout area efficiency has to take second priority over a highly crafted layout relying on pattern regularity, area density uniformity, unidirectional gates, and a multitude of other concerns in order to achieve IC manufacturability.