While the L-EDIT layout grid can be set to any conventional layout grid, it is sometimes helpful in deep nanoscale analog CMOS designs to not always use minimum grid settings or minimum design rules. Some examples of these instances include minimum metal spacing, contact-to-gate spacing, gate extension, etc. If the combination of coarser-than-minimum grid and more restrictive design rules can be used, the layout is less prone to DRC errors and some of the complex 2D design rules can be eliminated. In such case it is helpful for the designer to create a more-restrictive rule set than the minimum design rules permit. The creation of custom restrictive design rules is now being recommended for deep nanoscale CMOS designs by several authors. As is now well understood, ‘DRC correct’ no longer ensures manufacturability.

Does L-EDIT work acceptably well with the very fine-grid resolutions typical of deep-nanoscale layout.