Just the type of insight we need to fire up the dbaete.

Well, I am totally agree with your statement, and i am looking forward for tool regarding standard component of L-EDIT.

For complex analog CMOS circuits using any layout tool, the designer must always take care to create a very data-efficient hierarchical design. One problem which must be overcome is the high data transfer time between the layout and the tools required to verify the layout that may be running on computers in a remote facility. The circuit designer can also contribute to this data-efficiency effort if extensive re-use of sub-circuits is possible. If hierarchical layer generation is required, Tanner is developing a tool which will soon be available as a standard component of L-EDIT.

Does L-EDIT work well with the high data content typical of complex nanoscale analog CMOS designs?