Parasitic Extraction - HiPer PX | Tanner EDA
HiPer PX ensures successful IC tapeouts by providing accurate, simulation-ready RC models of interconnect parasitics and crosstalk.
HiPer PX is an accurate layout-to-circuit extractor for deep submicron MOS and bipolar circuits. Compact and accurate RC models for interconnects are generated that are accurate up to a user-defined signal frequency. HiPer PX uses a fast and comprehensive interpolation method or an accurate boundary-element method for capacitance extraction and an efficient finite-element method to accurately extract interconnect resistances.
Top features & benefits:
Designer can accurately model interconnect parasitic effects so they don't have to:
- Sacrifice performance or overdesign to achieve safety margins. This wastes power, silicon, and ultimately higher design time.
- Estimate parasitics by hand, which is laborious and inaccurate.
- Redesign if the design fails or is below specifications after fabrication. This leads to huge costs for failure analysis, redesign, fabrication and schedule loss.
2D (fast) extraction pre-computes a table of values using the same methods as the 3D version, and then uses that table to estimate the parasitics based on a 2D representation of the layout.
3D (accurate) extraction creates a full 3D model of the layout and extracts parasitics based on finite element analysis using the vertical spacing, thickness, and dielectric constant of the layers.