HiPer Simulation extends the capabilities of T-Spice Pro, Tanner EDA’s design entry and circuit simulation system, with support for Verilog-A, allowing designers to be more productive and accurate.

Verilog-A allows designers to describe and simulate analog circuits behaviorally, it enables a top-down approach to circuit design, and allows co-simulation between behavioral blocks and device level analog netlists. For model developers, Verilog-A provides an efficient language for describing device behavior which is portable across simulators.

HiPer Simulation is compliant with all Verilog-A specifications in the latest standard Verilog-AMS LRM (Language Reference Manual) version.

HiPer Simulation allows you to enhance your simulations so that you can:

• Run system level simulations early in the design cycle to find integration issues and minimize redesigns late in the design cycle.

• Perform special measurements such as DNL, INL, and relative settling time.

• Run Safe Operating Area checks during simulation, including whether a voltage is in range or if a device is operating in the specified region.

• Mix and match device level and behavioral representations of the blocks for faster run times.

• Easily create complex input stimuli such as random signals, pseudo-random bit streams, and signals that are clipped, non-linearly compressed, or sampled.

• Create your own models for unusual devices such as TFTs, Image Sensors, Solar Cells, Thyristors, or EMS devices using a simple and efficient language for describing device behavior.

Verilog A

Verilog-A allows designers to describe and simulate analog circuits behaviorally, it enables a top-down approach to circuit design, and allows co-simulation between behavioral blocks and device level analog netlists. For model developers, Verilog-A provides an efficient language for describing device behavior which is portable across simulators.

HiPer Simulation is compliant with all Verilog-A specifications in the latest standard Verilog-AMS LRM (Language Reference Manual) version.

Verilog-A enables behavioral design and simulation of analog circuits, proving system level designs before committing to full device-level design.

T-Spice with Verilog-A enables model developers to specify compact models in a high level language, and T-Spice’s compiled approach minimizes the performance difference compared to simulator-specific C-models.

Top 4 features & benefits:

1. Behavioral modeling for faster runtimes and early system level simulations
2. Enables special checks and measurements making designers more productive and accurate. Catch errors early for minimal impact.
3. Create complex input stimuli to mprove productivity and perform special analysis like transient noise analysis
4. Facilitates model creation of non‐standard devices such as MEMS, image sensors, or TFTs