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Analog IC, Mixed Signal Design Verification - HiPer Verify | Tanner EDA

IC design is an increasingly complex task with mounting competitive pressures.  Fast cycle time and error-free tape-out require an efficient workflow and rapid design verification iterations.

Tanner EDA's HiPer Verify is a comprehensive yet affordable solution for analog/mixed signal IC design rule checking (DRC) and layout versus schematic checking (LVS). The tool uses advanced hierarchical algorithmic techniques to provide optimal performance for your designs and can meet the most challenging submicron verification requirements.

Tanner EDA's HiPer Verify physical verification tool:

HiPerVerifyResults

Integrates with Other Tools to Reduce Risk and Uncertainty
  • Can co-exist with sign-off tools like Calibre® and Assura® to provide access to verification tools throughout the design cycle to mitigate risk and uncertainty

  • Provides a more affordable solution when the high price of time-based or TBL "gold standard" physical verification tools require saving verification until the end of design and layout

View the datasheet on Tanner EDA's EVI tool for Calibre integration

Increases Productivity
  • Designed to take advantage of hierarchy and repetition in today's IC designs

  • Hierarchical rule checking engine finds violations in the cell where they occur, enabling one-time correction rather than sorting through duplicate violations as required by flat processing
  • Integrated with L-Edit, HiPer Verify enables layout engineers to run DRC on their layout in a single click and see errors one by one instead of waiting for an entire run to finish checking an entire design.

Finds and Fixes Violations Quickly

  • An advanced Verification Error Navigator takes you instantly to the location of a violation in the layout editor and provides a clear and thorough summary report of DRC results

  • Verification Error Navigator opens the cell and centers the layout exactly on the selected violation, making it easy to see and correct

Compatible with Foundry Verification Decks

  • HiPer Verify can run Calibre® and Dracula® rule files directly from the foundry

  • Switching to a new rule deck is easy with HiPer Verify, whether it's an update of your existing process or switching to a whole new process.  Just reference the new command file from the foundry, and you're ready to go.
  • Offers the security of knowing you are running your rule files without modification or conversion, and the convenience of not having to perform translations.

 

Download the HiPer Verify Datasheet

 

 

Calibre is a registered trademark of Mentor Graphics.  Assura and Dracula are registered trademarks of Cadence Design Systems, Inc.

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