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Tanner EDA Software Tools - Training Course Outline for Analog IC & Mixed Signal Design

Tanner EDA offers high-quality training to keep you ahead in the IC design world. Our instructors have extensive designing experience to help bridge the gap between how Tanner Tools work and how they can best work for you. This training course covers the entire HiPer Siliconâ„¢ design flow, including S-Editâ„¢ for schematic capture, T-Spiceâ„¢ for simulation, L-Editâ„¢ for layout, and HiPer Verifyâ„¢ for verification.  Sign up for just our front end training using S-Edit, T-Spice, and W-Edit (Day 1 & 2), basic layout using L-Edit (Day 3), advanced layout using L-Edit (Day 4 & 5) or take our full flow training (5 days).

Day 1: Front End Design with S-Edit
9:00 a.m. to 5:30 p.m.

  • Creating & Managing Designs
  • Schematic & Symbol Editing
  • Properties & Evaluated Properties
  • Libraries
  • Automatic Symbol Generation
  • Buses & Arrays
  • Simulation & Waveform Cross-Probing
  • Back-Annotation of Operating Point Results

Day 2: Analog Simulation with T-Spice & W-Edit
9:00 a.m. to 5:30 p.m.

  • T-Spice Simulation & Analysis
  • Integration Methods for Transient Simulation
  • Parameter Analysis
  • Virtual Measurement using .MEASURE
  • Handling Convergence Issues
  • Accuracy Control & Table Mode Simulation
  • Optimization
  • Special Applications

Day 3: IC Layout with L-Edit
9:00 a.m. to 5:30 p.m.

  • Introduction to L-Edit
  • Layout Polygon & Cell Handcrafting
  • Boolean Operation, Object Snapping & Base Points
  • Interactive DRC
  • Creating & Managing Designs
  • Special Operations for Enhanced Productivity
  • Cross-section Viewing
  • Setting up Layers & Generating Layers
  • Introduction to T-Cells & the User Programmable Interface (UPI)
  • Tape-out

Day 4: Schematic Driven Layout, DRC, & Netlist Extraction
9:00 a.m. to 5:30 p.m.

  • Automatic Via Placement & Guard Ring Generation
  • Schematic Driven Layout (SDL)
  • PDKs
  • Standard DRC
  • Browsing & Fixing DRC violations
  • Design Rule Setup & Optimization
  • HiPer – Using Calibre® & Dracula® Command Files
  • Netlist Extraction

Day 5: Node Highlighting, LVS, & Place & Route
9:00 a.m. to 5:30 p.m.

  • Node Highlighting
  • Layout vs. Schematic Check & Debug
  • Standard Cell Place & Route (SPR)
  • Creating Standard Cells
  • Top Level Chip Assembly
  • Full Chip Verification

Contact Sales

+1-626-471-9701

+1-877-325-2223

sales@tannereda.com

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