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Accelerated Analog Design Layouts - HiPer DevGen | Tanner EDA


Break through the analog design and layout bottleneck!

The iterative and highly artistic nature of analog design and layout has traditionally been considered to be more difficult than digital layout. Not surprisingly, digital design automation has advanced at a much faster pace than its analog counterpart; resulting in analog design layout becoming a bottleneck to faster time-to-market.

HiPer DevGen - Tanner EDA's new game-changing tool - accelerates rather than automates the environment; maintaining the artistic nature of the process while allowing engineers to meet market demands for quality and cycle time.



Easy to Set-up and Use

  • Easy integration with existing design flows with no change in methodology
  • Works with unmodified schematics
  • Can be driven by any netlist through schematic driven layout (SDL) in L-Edit.
  • Builds upon Tanner's existing T-Cell architecture of parameterized cells that exist within L-Edit.
  • User-friendly GUI - no CAD development required
  • 20 minutes for any new process!


Recognizes and Generates Common Structures

  • Differential pairs
  • - Multiple options to ensure matching, optimized parasitic, add dummy devices, guard rings and antenna effect diodes, etc.

  • Current mirrors
  • - Multiple outputs of different current strengths, options to ensure matching, add dummy devices, share diffusion and match STI effects.

    - Multiple finger with options for gate and bulk connections and adjustments for well proximity effects.

  • Resistor dividers

Primitives are often the most time-consuming aspect of layout and specifically the parts that are critical to the functionality of the silicon. The HiPer DevGen tool applies matching techniques to address common processing artifacts, produces the optimal solution for parasitic and silicon area, and creates devices optimized for high yield. Layout engineers have complete freedom over generation options, layout, placement, and routing of these structures.



Correct by Construction

  • Closely aligned to handcrafted layout
  • Uses only the manufacturing design rules for the specific technology node as input. It is possible to very quickly move a design to a new technology node or to a different foundry
  • DRC and LVS clean


Consistent High Quality

  • Guarantees design standards are the same across the organization


"Silicon Aware"

  • Understands functionality and process artifacts



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