Tanner Tools V13.0 Available Now 
Tanner Tools version 13.0 has been released and is available for download. Read on for a summary of the new products and features added to our latest release.
HiPer Verify
HiPer Verify is a comprehensive yet affordable solution for analog/mixed signal IC design rule checking (DRC) and netlist extraction.
Most foundries provide DRC and LVS rules in Calibre or Dracula® format. When you change your process or feature size, you must update your DRC & LVS rules—a time-consuming process.
HiPer Verify can run Calibre and Dracula command rule files, for DRC and netlist extraction, directly from the foundry. When your verification process changes, you can simply reference the new DRC or LVS command rule file from the foundry, meeting your existing standards right out of the box. You get the security of knowing you are running your rule files without modification or conversion, and the convenience of not having to perform translations.
As an available option, HiPer Verify is included with HiPer Verify Pro, HiPer Design and HiPer Silicon packages.
Click here for more details.
Verilog-A
T-Spice now incorporates a full Verilog-A implementation, enabling designers to easily and quickly write their own custom behavioral models for early system level simulations. T-Spice is compliant with all Verilog-A specifications in the latest standard Verilog-AMS LRM (Language Reference Manual) version 2.2, passes the Compact Model Council test suite, and is fully compatible with Spectre®, HSPICE, and SmartSpice.
As an available option, the Verilog-A support is included with HiPer Simulation and HiPer Silicon packages.
Click here for more details. HiPer PX
HiPer PX is a new 3D physics-based parasitic extraction tool that extracts devices and creates compact and accurate RC models for interconnects up to a user-defined signal frequency. HiPer PX uses a fast and comprehensive
interpolation method or an accurate but efficient boundary-element method for capacitance extraction. It uses an
efficient finite-element method to accurately extract interconnect resistances.
HiPer PX is fully integrated within L-Edit, ensuring ease of use and minimal training time. It is available in two variants: HiPer PX2D extracts parasitics using a fast interpolation method for estimation of parasitics, and HiPer PX3D uses a highly accurate 3D boundary-element method to extract parasitic capacitances.
- Extracts 2D interconnect resistance and capacitance for fast extraction times and 3D RC for more accurate parasitic extraction
- Output is a simulation-ready SPICE netlist of devices and RC parasitics
- Supports reduction of RC networks based on a user-specified time constant
As a superset, HiPer PX 3D Parasitic Extraction includes all the capabilities of HiPer PX2D. A license of L-Edit is required to run HiPer PX products.
Click here for more details. S-Edit
S-Edit enables schematic capture for the most complex full custom IC design. This easy-to-use PC-based design environment for schematic capture integrates tightly with Tanner EDA’s simulation, physical layout, and verification tools.
New features for S-Edit:
- Hierarchical Find - search for nets, instances and objects through the hierarchy.
- Hierarchy Navigator - quickly traverse your design hierarchy.
- Verilog netlists - import structural Verilog netlists.
Click here for more details. L-Edit
L-Edit is an advanced IC layout editor that meets your needs
by combining the fastest rendering
available with powerful features
that exceed the needs of the most
demanding user.
New features for L-Edit:
- Enhanced XrefCells - handles multiple levels of reference across multiple libraries.
- SDL enhancement - automatically updates flylines when moving instances.
- Enhanced Curved Tools - add equal width fillets to wires and fillets to curved objects.
Click here for more details.
A complete list of features and fixes in V13 can be found on the customer support site. Customer login required.
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What's New in v13.0 Live Demo
If you would like to see the new features in V13, we are hosting scheduled demonstrations, starting Thursday, April 17th. The web demo will consist of a short 10-15 minute overview of what’s new in v13.0, followed by a detailed demonstration (25-30 minutes) of the new capabilities in either the front-end or the back-end tools.
Scheduled Demo Dates:
- April 17th - What’s New in Tanner Tools v13 – overview & front-end
- April 24th - What’s New in Tanner Tools v13 – overview & back-end
- May 1st - What’s New in Tanner Tools v13 – overview & front-end
- May 8th - What’s New in Tanner Tools v13 – overview & back-end
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| Celebrating 20 Years of Customer Success
What were you doing in 1988?
Well, this was the year the Oscar winning film Rain Man was released. The Redskins won their second Super Bowl and Calgary hosted the Winter Olympics. This also happens to be the year John Tanner founded Tanner EDA with the goal of providing cost-effective, PC-based IC design tools for every professional engineer's desktop. Since then, award-winning products such as L-Edit, T-Spice and HiPer Verify have been streamlining the silicon design process for 20,000+ engineers and designers worldwide.
To celebrate our 20th anniversary year, we are offering a 20% discount on qualifying products and upgrades. Offer expires May 31st *
To find out more, call
(626) 471-9701,
or email your sales representative for details.
*Offer applies to commercial programs in North America only. |
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Migrating to Affordable Functionality
In an ever increasing competitive market, many businesses are finding it difficult to justify the exorbitant costs associate with so called “high-end” design systems having many features they will never use. An increasing number of IC designers are searching for an affordable alternative to the mainstream EDA tools. At least one option exists, offering flexibility and functionality, with vendor responsiveness a welcome extra.
One project group within a large research division of a major, multinational systems house, recently successfully migrated from a full suite of the most up-to-date Cadence IC design tools to the eminently affordable toolset from Tanner EDA. The switch was carefully planned and has proved not only highly effective, but relatively painless too.
"The team was impressed with the flexibility and ease of use of the tools, and especially with Tanner's responsiveness in terms of providing custom model support. In fact, they found it took much less time to set up the simulator and debug the models with Tanner than it had previously with Cadence."
Read the full article here.
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