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Noble Peak Case Study

How does an IC startup overcome the learning curve of high-end EDA tools?

NoblePeak Vision Corporation faced this challenge when developing its TriWave. imager, a germaniumenhanced CMOS imager at the core of its line of night-vision products used in security, transportation and defense.

ICs for Seeing in the Dark

The founders of NoblePeak Vision discovered a way to grow defect-free germanium on a silicon substrate in such a way that it is compatible with conventional CMOS processing. They developed the technology into a lowcost imager that extends the sensitivity of silicon cameras into the short wave infrared (SWIR) band to enable lowcost day/night vision.

With funding from the National Science Foundation, they designed a prototype 128x128 imager, then began designing a VGA version with venture funding.

NoblePeak Vision's approach is based on the longer wavelengths of Earth's natural night glow, which are far beyond those visible to low-light cameras. The TriWave imager takes advantage of germanium's sensitivity to longer wavelengths to reach past nearinfrared spectrum into SWIR spectrum. The CMOS imager in TriWave is primarily analog, with some digital circuitry for timing, setup and control of the analog circuits.

While TriWave is a vertical application, NoblePeak Vision intended to design it for the manufacturing advantages of a standard CMOS foundry; namely, high volume, high quality, low costs and global semiconductor infrastructure.

First, The Budget

"From the beginning we wanted a complete tool set that would get us off the ground without blowing the limitations of our venture funding," explains Bryan Ackland, vice-president of engineering for NoblePeak Vision. "It's not hard to find a more affordable tool for, say, schematic capture and another for verification, but we really wanted a suite of tools for our entire analog design flow with tools for digital design as well."

"In a startup, where you wear different hats every day and spend only some of your time doing IC design, the learning curve on most high-end tools is just enormous. The user interface on Tanner EDA tools is much more task-oriented and intuitive."

-Bryan Ackland
VP Engineering
NoblePeak Vision Corporation

"We were a few months into trying a different, high-end suite, but we realized we were spending too much time learning how to use it. Then, when we started looking at Tanner's EDA tools, we couldn't get over how simple and intuitive they were compared to the first product." While NoblePeak Vision also licensed some expensive point tools from other suppliers, the Tanner tools met their need for ease of use at the right price.

Demanding Application, Timely Response

The total number of cells in the imager is not very high for an analog design, and the variety of cells (circuits beyond the pixels, row and column decoders, amplifiers) is not that great, but the pixels are replicated hundreds of thousands of times in an array. This led to problems with design rule checking (DRC).

When checking its physical chip layout against foundry design rules, the engineers found that the pixel replication in the VGA version of the imager slowed Tanner's DRC and Layout Versus Schematic (LVS) tools dramatically. When they contacted Tanner about the performance problem, Tanner jumped at the chance to use a customer's design to optimize its DRC and LVS code. Within a few weeks, Tanner had lowered DRC run time on the extremely repetitive imager to about one hour. In the meantime, NoblePeak Vision resorted to a point tool for LVS and DRC on the chip, but stuck with the Tanner tools for design because of their ease of use.

"The menus and options [of some high-end point tools] are extensive, but they come with learning overhead that our staff just can't afford."

Ackland believes that the cooperation paid off. "It was in our interest to help Tanner improve the run time because we wanted to be able to use the tools on an ongoing basis, and we were able to provide specific case examples so that they could tune their code."

Six Months On, Six Months Off

As a startup, NoblePeak Vision has to run as efficiently as possible. Besides sitting down with EDA tools and designing ICs, engineers meet with customers, work on evaluation kits and set up test environments. Furthermore, the development team focuses about six months of the year on design and the other six months away from design–working with camera partners, defining test scenarios, and improving yield and reliability in existing products.

Without dedicated, full-time staff to set up manufacturing files and libraries, different engineers at NoblePeak Vision need to pick up the tools and make them productive almost immediately.

"High-end tools can be very powerful and have a huge number of options," continues Ackland, "and we use them for a few specific tasks, but their user interface doesn't emphasize task priority or workflow or frequency of use. We also like the fact that Tanner's EDA tools are PC-based, because we tend to learn the tools and work better in that more intuitive environment."

Plays Well With Others

Like many designers who use highend point tools for specific tasks in designing hybrid analog-digital ICs, NoblePeak Vision relies on the Tanner EDA suite for smooth integration.

The VGA imager had much more digital circuitry than the 128x128 prototype, so alongside of workstationbased tools for synthesis and placeand- route, NoblePeak Vision used Tanner's PC-based tools for assembly. Bridging designs (analog and digital), platforms (PC and workstation) and toolsets, the engineers saw plenty of potential for inefficiency.

"When we set out to do the VGA design," Ackland recalls, "we knew we could depend on the Tanner tools for all of our work in analog. We planned to design the analog blocks on Tanner tools, and then perform most of the chip assembly on workstation tools. But we were so used to working in the more intuitive Tanner world that we ended up doing the entire chip assembly in Tanner. We designed the digital block on the workstation, then transferred it to Tanner as a GDS file for all of our chip assembly. We then moved it back to the workstation for final checks."

"I think other companies in our position move back and forth between platforms and tools like this as well. We've been successful in partitioning between Tanner and other tools because Tanner handles the GDS files we transfer at different points in our workflow. If we had to rely on the ability of these tools to understand each other's databases, we could never work with this kind of agility."

Icing on the Cake

NoblePeak Vision's engineers used the tutorials in the Tanner tools to explore functionality and get up to speed quickly. The suite goes far beyond the design process by providing files that IC designers do not want to spend valuable time creating themselves, such as foundry technology files and I/O pads.

"We reached all of the goals for our first round of venture funding, and meeting those goals helped us get our second round of funding. Tanner EDA tools have been an important part of those achievements. They've been the right tools matched to the right people and skill sets".

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