Tanner Tools for Verification

HiPer Verify

HiPer Verify offers IC, MEMS and integrated optical device designers high performance tools for design creation with foundry compatibility for reliable hierarchical design rule checking.

HiPer Verify is design rule checking that meets the most challenging submicron requirements while supporting a broad range of technologies for analog, mixed signal and MEMS applications.

• Hierarchical foundry-compatible rule support allows HiPer Verify to run Calibre® and Dracula® foundry files natively, without conversion or modification.
• Background DRC allows design and editing to continue while DRC is running.
• DRC Error Navigator displays results in real time, so users can examine and fix errors while the DRC job is still running.
• Integration with L-Edit Layout Editor for quick turnaround of results and precise location of errors.

L-Edit Standard DRC

• An all-angle, hierarchical design rule checker capable of verifying your most challenging designs.
• Easy and quick setup with its user-configurable rule setup for any technology and its intuitive graphical interface.
• Precise error location: Hierarchical error output displays errors at the level of the hierarchy where they occur. The error navigator opens the cell and zooms automatically to the location of the error.
• Import Calibre® DRC results for browsing in L-Edit Layout Editor.

L-Edit Layout versus Schematic (LVS)

• Accurately and efficiently compares two SPICE netlists to determine if they contain equivalent circuit descriptions.
• Supports a full range of pre-processing options to optimize netlists for comparison such as merging parallel/series devices, removing parasitics, shorting or opening devices.
• Checks for soft-connections to increase your yield.
• Supports T-Spice, HSPICE, PSpice and CDL formats.

L-Edit SPICE Netlist Extract

• Generates a SPICE netlist from L-Edit layout for LVS comparison or for post layout simulation with T-Spice.
• Ability to label devices and nodes allows rapid searching of elements in the layout to aid in verification against schematic.
• Parasitic node capacitances can be extracted, including fringing effects, for increased accuracy.
• Extracts active and passive devices and user-definable subcircuits, with support for 90° and 45° objects.
• Extraction of the most common device parameters includes:
  • MOSFET width, length, source/drain area and perimeters
  • Areas of diodes, BJTs, MESFETs, and JFETs
  • Hierarchical subcircuit extraction for functional blocks
  • Capacitance and resistance

HiPer PX Parasitic Layout Extraction

HiPer PX is an accurate layout-to-circuit extractor for deep submicron MOS and bipolar circuits. It uses an efficient finite-element method to accurately extract interconnect resistances. Compact and accurate RC models for interconnects are generated that include higher-order moments and that are guaranteed to be accurate up to a user-defined signal frequency.

HiPer PX supports reduction of RC networks based on a user-specified time constant. This results in a minimal netlist which accurately models circuit performance up to the highest frequency the designer is concerned with.

HiPer PX 2D

• For fast and efficient boundary element estimation of parasitics
• Estimates parasitics based on pre-computed table of values.
• 2D parasitic extraction can be run hierarchically or flat.

HiPer PX 3D

• Highly accurate extraction creates a full 3D model of the layout and extracts parasitics based on finite element analysis using the vertical spacing, thickness, and dielectric constant of the layers.

L-Edit Node Highlighting

• Enhances verification by providing connectivity visualization so you can quickly find and fix layout versus schematic problems.
• View multiple nodes in different colors to track down shorts and opens.