HiPer Silicon gives the designer a complete analog design flow from schematic capture, circuit simulation, and waveform probing to physical layout and verification, which is ideal for analog, mixed-signal, RF and MEMS IC design.

This integrated tools suite shares a common architecture and common User Interface that is consistent across all tools, resulting in a comprehensive, unified software solution that maximizes design productivity while simultaneously reducing total cost of ownership. HiPer Silicon’s advanced features improve designer productivity, including Verilog-A simulation, device layout automation, interactive autorouting, foundry-compatible physical verification and parasitic extraction.

Schematic Capture: S-Edit

S-Edit is an easy-to-use design environment for schematic capture and it gives you the power you need to handle your most complex full custom IC design capture.

• S-Edit’s tight integration with SPICE simulation allows viewing operating point results directly on the schematic and performing waveform cross-probing to view node voltages and device terminal currents or charges.
• S-Edit imports schematics via EDIF from third party tools, including Cadence, Mentor, Laker, ORCAD and ViewDraw with automatic conversion of schematics and properties for seamless integration of legacy data.
• S-Edit’s schematic design checks enables you to check your design for common errors such as undriven nets, unconnected pins and nets driven by multiple outputs so you can catch errors early before running simulations.

Analog Simulation: T-Spice & W-Edit

T-Spice performs fast, accurate simulations for analog and mixed-signal IC designs and fully supports foundry models for reliable and accurate simulations.

• T-Spice offers HSPICE® and PSpice® compatible syntax and supports the latest industry models, including PSP, BSIM3.3, BSIM4.6, BSIM SOI 4.0, EKV 2.6, MOS 9, PSP, RPI a-Si & Poly-Si TFT, VBIC, and MEXTRAM models to allow easy integration of legacy designs and foundry models.
• T-Spice lets you precisely characterize circuit behavior using virtual data measurements, Monte Carlo analysis, and parameter sweeping.
• T-Spice supports Verilog-A for analog behavioral modeling, allowing designers to prove system level designs before doing full device level design.
• View the T-Spice Datasheet.

Physical Layout: L-Edit

L-Edit is a complete hierarchical physical layout editor combing fast rendering and built-in productivity tools to let you maximize your efficiency when creating the layout for your design.

• Take full advantage of L-Edit’s optimized editing which allows you to edit layout with fewer mouse clicks than any other layout editor, for maximum efficiency.
• Speed up design cycles with built-in productivity tools such as object snapping, alignment tools, automatic guard ring generation, complex boolean operations on objects or layers, and cross-probing between schematic and layout.
• L-Edit supports parameterized cells allowing you to create automatic custom layout generators or use DevGen to easily setup layout generators for most common devices such as MOSFETs, resistors, or capacitors.
• L-Edit’s built-in Interactive DRC displays violations in real time while you edit your layout, helping you create compact, error-free layouts the first time.
• L-Edit’s Node Highlighting capability allows you to highlight all geometry connected to a node so you can quickly find and fix LVS problems such as shorts and opens.

View the L-Edit Datasheet

Schematic Drive Layout: SDL & SDL Router

SDL is integrated with the L-Edit Layout Editor and provides tools to increase the speed and quality of custom layout by allowing the designer to manage the routing flow and to focus on layout quality.

• SDL imports a netlist from any schematic tool and automatically instances all needed subcells, including parameterized cells using the parameters associated with each device in the netlist.
• SDL displays flylines allowing you to place your blocks to minimize routing congestion.
• SDL can perform engineering change orders (ECO) and highlight differences in the netlists for faster layout of design changes.

• SDL Router allows the designer to focus on routes that require expensive hand craftsmanship for performance or addressing analog-sensitive nets or parts of nets, then letting the SDL Router automatically route the non-critical nets.
• SDL Router can route different nets with different user specific widths with support for multiple vias used for layer transitions.
• SDL Router allows designers to mark existing geometry as part of a specific net allowing selection, highlighting, and rip-up of geometry by net to capture the designer’s intent.

Physical Verification: HiPer Verify

HiPer Verify is a comprehensive yet affordable solution for analog/mixed signal IC design rule checking (DRC) and netlist extraction.

• HiPer Verify runs Calibre®, Assura®, and Dracula® foundry files natively, without conversion or modification.
• HiPer Verify’s hierarchical rule checking engine finds violations in the cell where they occur, enabling you to correct a violation once rather than sorting through many duplicate violations as flat processing requires.
• HiPer Verify is integrated with the L-Edit Layout Editor, allowing for precise location of errors, quick turnaround of corrections, and faster debugging.

Physical Verification: HiPer PX

HiPer PX is a high performance parasitic extraction tool that is integrated with Tanner’s L-Edit layout editor for easy and rapid extraction of parasitics.

• HiPer PX quickly extract simulation-ready SPICE netlists from layout, including devices (MOSFETs, bipolars, etc) and interconnect parasitics.
• HiPer PX extract accurate, complete parasitic networks for each node, including vertical and lateral coupling capacitance and interconnect resistance.
• HiPer PX can simplify the parasitic RC network without reducing simulation accuracy up to a user-specified frequency with the built-in netlist reduction algorithm.

View the HiPer PX Datasheet