Industry-leading Productivity for Analog, Mixed Signal and MEMS Layout from Tanner EDA
With time-to-market and design spins at a premium, designers and engineers need a layout editor that delivers fast rendering and high productivity. To compete in a high-efficiency, high-productivity marketplace, you need a toolset that has proven its ability to accelerate your design cycle.
Built on our hallmark layout editor, L-Edit, Tanner EDA's back end design packages meets your needs by combining the fastest rendering available with powerful features that exceed the needs of the most demanding user. Whether you are creating analog or mixed signal ICs, MEMS, or sensors, this leading design tool enables you to get started with minimal training. You can draw and edit quickly, with fewer keystrokes and mouse clicks than other layout tools. Using powerful features such as object snapping, boolean operations, and alignment tools, you can work more efficiently to save time and money.
Our L-Edit IC package includes L-Edit for layout editing, Interactive DRC for real-time design rule checking during editing, and Node Highlighting for highlighting all geometry associated with a node. It also includes our Standard Device Generator for design primitives, Schematic Driven Layout that creates layout directly from the schematic, and I/O pad cross-reference export tool to facilitate packaging tasks. Click here to view the datasheet for L-Edit and related products in this package.
For Engineers and Designers looking for even greater productivity, Tanner EDA offers two additional packages that extend our L-Edit IC capabilities; HiPer L-Edit DevGen and HiPer L-Edit Router.
HiPer L-Edit DevGen provides all of our L-Edit IC capabilities and adds on HiPer DevGen; our layout acceleration tool. HiPer DevGen recognizes and generates common analog structures such as Differential Pairs, Current Mirrors and Resistor Dividers. Click here to read more about HiPer DevGen
HiPer L-Edit Router combines our high-performance L-Edit IC package with our SDL Router, a general area based router ideal for top-level chip assembly; offering unparalleled workflow productivity for engineers doing layout routing.
HiPer Place & Route (P&R) is a right-size place and route solution for Big Analog/Little Digital mixed-signal design, offering excellent performance, ease of use, and value. HiPer P&R is optimized for analog specialty process technologies on the 90-350nm nodes, with 10-50k gates of digital logic. HiPer P&R is highly flexible, allowing the user unparalleled flexibility during every phase of the flow.