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Tanner EDA Product Comparison Chart

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Full Flow

included in package  Optional Add On

Product / Package
S-Edit: Schematic Capture S-Edit is an easy-to-use Windows or Linux-based design environment for schematic capture. It gives you the power you need to handle your most complex full custom IC design capture. S-Edit is tightly integrated with Tanner EDA's T-Spice™ simulation, L-Edit™ layout, and HiPer™ verification tools. It is also integrated with the Analog FastSPICE plug-in from Berkeley Design Automation.
W-Edit: Waveform Editor W-Edit provides an intuitive multiple-window, multiple-chart interface for easy viewing and analyzing waveforms and data in highly configurable formats.
T-Spice: Spice Simulation T-Spice offers HSPICE® and PSpice® compatible syntax and supports the latest industry models, including PSP, BSIM3.3, BSIM4.6, BSIM SOI 4.0, EKV 2.6, MOS 9, PSP, RPI a-Si & Poly-Si TFT, VBIC, and MEXTRAM models to allow easy integration of legacy designs and foundry models.
Verilog-A: Behavioral Modeling T-Spice provides extensive supportof behavioral models using Verilog-A,expression controlled sources, and table-mode simulation. Behavioral models give you the flexibility to create customized models of virtually any device.
Berkely Design Automation T-AFSBDA's Analog FastSPICE is now integrated with Tanner's S-Edit schematic capture and W-Edit waveform analyzer giving you unprecedented speed in a powerful, easy-to-use design system. Users can drive the T-AFS simulator directly from S-Edit getting all of the speed and accuracy necessary for nanometer design. Simulation results are displayed automatically in W-Edit for viewing, measuring, and analyzing interactively.
Verilog-AMS: Mixed-Signal AnalysisTanner EDA's HiPer Simulation AMS and HiPer Silicon AMS packages include Verilog-AMS; a derivative of the Verilog hardware description language.  It includes both analog and mixed-signal extensions that enable a designer to define the behavior of analog and mixed-signal (AMS) systems.
Aldec Riviera-PRO: Digital SimulatorRiviera-PRO TE (Tanner Edition) delivers advanced design entry, simulation, debugging and verification tools for digital Designers. It is available for Linux and Windows platforms.
L-Edit: Layout EditorTanner EDA's L-Edit Pro combines the fastest rendering available with powerful features that exceed the needs of the most demanding user. This leading analog/mixed signal IC design tool enables you to get started with minimal training. You can draw and edit quickly, with fewer keystrokes and mouse clicks than other layout tools.
Interactive DRC: Design Rule CheckerInteractive DRC displays the spacing distance of a design in real time while the layout is edited; helping to create compact, error-free layouts ad providing real-time design rule checking during editing.
Node HighlightingNode Highlighting helps to quickly visualize node connectivity - helping to quickly find and fix LVS problems.
Pad MapThis Pad IO cross-reference extractor tool generates bonding reports and creates bonding diagrams for packaging.  It also facilitates design data exchange from L-Edit to Altium PCB solutions.
Schematic Driven LayoutSchematic Driven Layout (SDL) encourages good design practices by keeping close synchronization between the schematic and the layout. Names of devices, cells and nets will be automatically set. Drawn routing is automatically labeled with the net name for easy inspection and management.SDL increases productivity and eliminates errors with automatic instancing of cells and parameterized devices. If device parameters change later, parameterized cells will be automatically updated.
Device Generator - StandardTanner's Standard Device Generator offers designers the ability to create basic cell constructs to improve productivity and quality of design.
SDL RouterSDL Router is an automatic routing engine integrated directly into SDL. It speeds layout by automatically routing non-critical nets while allowing the designer to manually route performance sensitive nets and parts of nets. It natively uses the routing geometry created by the user, and runs on all or a specified subset of nodes on each pass. SDL integration means users can easily highlight and rip up nodes, manage the manual and automatic routing status, and implement ECOs
HiPer DevGenTanner's High Performance Device Generator accelerates analog layout by generating several core design elements including current mirrors, differential pairs, resistor dividers and MOSFETs.
DRC-StandardTanner EDA's standard Design Rule Checking (DRC) offers designers an automated tool for verifying the correctness of a mask set.
Extract-StandardStandard Extract generates a flat SPICE netlist from layout for LVS or post-layout simulation
LVS-StandardStandard LVS accurately and efficiently compares two SPICE netlists to determine whether they contain equivalent circuit descriptions including merging of devices and matching of device parameter values.
HiPer Verify (DRC & Extract)Tanner EDA's HiPer Verify™ is a comprehensive yet affordable solution for analog/mixed signal IC design rule checking (DRC) and layout versus schematic checking (LVS). The tool uses advanced hierarchical algorithmic techniques to provide optimal performance for your designs and can meet the most challenging submicron verification requirements.
DXF Import/ExportDXF Import/Export facilitates file sharing and tool interoperability for improved productivity.
Curve ToolsTanner EDA's curve tools add-in is a chamfers and fillets generator for all-angle objects.
HiPer PX - 2DHiPer PX facilitates accurate modling of interconnect parasitic effects.  2D (fast) extraction pre-computes a table of values using the same methods as the 3D version, and then uses that table to estimate the parasitics based on a 2D representation of the layout. 2D can be run hierarchically or flat
HiPer PX - 3DHiPer PX facilitates accurate modling of interconnect parasitic effects. 3D (accurate) extraction creates a full 3D model of the layout and extracts parasitics based on finite element analysis using the vertical spacing, thickness, and dielectric constant of the layers. 3D extraction can only be run in flat mode.
Incentia DesignCraft:  SynthesisThe integrated DesignCraft logic synthesis tool offers optimization for area, power, timing and design-for-testability (DFT). DesignCraft offers Verilog/VHDL, SDC, NLDM .lib / CCS compatibility. This proven tool offers fast runtimes - typically 5M gates within 2 hours.
Incentia TimeCraft: Functional VerificationTimeCraft-SI is Incentia's high-speed, big-capacity, signal integrity (SI) analysis tool, built on top of Incentia TimeCraft STA tool and integrated into Tanner's Mixed Signal design flow. Proven through customer tape-outs, TimeCraft-SI offers an integrated STA and SI analysis solution.
SoftMEMS 3D Solid ModelerThe SoftMEMS 3D Solid Modeler is integrated with Tanner's L-Edit MEMS and L-Edit MEMS Designer packages. It creates a 3D view of a MEMS device from a selected layout area and fabrication process description.
HiPer Silicon
 
 
 
 
 
HiPer Silicon AMS
 

Front End

 included in package  Optional Add On

Product / Package
S-Edit: Schematic Capture S-Edit™ is an easy-to-use Windows or Linux-based design environment for schematic capture. It gives you the power you need to handle your most complex full custom IC design capture. S-Edit is tightly integrated with Tanner EDA's T-Spice™ simulation, L-Edit™ layout, and HiPer™ verification tools. It is also integrated with the Analog FastSPICE plug-in from Berkeley Design Automation.
W-Edit: Waveform Editor W-Edit provides an intuitive multiple-window, multiple-chart interface for easy viewing and analyzing waveforms and data in highly configurable formats.
T-Spice: Spice Simulation T-Spice offers HSPICE® and PSpice® compatible syntax and supports the latest industry models, including PSP, BSIM3.3, BSIM4.6, BSIM SOI 4.0, EKV 2.6, MOS 9, PSP, RPI a-Si & Poly-Si TFT, VBIC, and MEXTRAM models to allow easy integration of legacy designs and foundry models.
Verilog-A: Behavioral Modeling T-Spice provides extensive support of behavioral models using Verilog-A,expression controlled sources, and table-mode simulation. Behavioral models give you the flexibility to create customized models of virtually any device.
Berkely Design Automation T-AFSBDA's Analog FastSPICE is now integrated with Tanner's S-Edit schematic capture and W-Edit waveform analyzer giving you unprecedented speed in a powerful, easy-to-use design system. Users can drive the T-AFS simulator directly from S-Edit getting all of the speed and accuracy necessary for nanometer design. Simulation results are displayed automatically in W-Edit for viewing, measuring, and analyzing interactively.
Verilog-AMS: Mixed-Signal AnalysisTanner EDA's HiPer Simulation AMS and HiPer Silicon AMS packages include Verilog-AMS; a derivative of the Verilog hardware description language.  It includes both analog and mixed-signal extensions that enable a designer to define the behavior of analog and mixed-signal (AMS) systems.
Aldec Riviera-PRO: Digital SimulatorRiviera-PRO TE (Tanner Edition) delivers advanced design entry, simulation, debugging and verification tools for digital Designers. It is available for Linux and Windows platforms.
HiPer Simulation
 
 
 
HiPer Simulation T-AFS
 
 
HiPer Simulation AMS
 
T-Spice Pro
 
 
 
 

Back End

 included in package  Optional Add On

Product / Package
L-Edit: Layout EditorTanner EDA's L-Edit Pro combines the fastest rendering available with powerful features that exceed the needs of the most demanding user. This leading analog/mixed signal IC design tool enables you to get started with minimal training. You can draw and edit quickly, with fewer keystrokes and mouse clicks than other layout tools.
Interactive DRC: Design Rule CheckerInteractive DRC displays the spacing distance of a design in real time while the layout is edited; helping to create compact, error-free layouts ad providing real-time design rule checking during editing.
Node HighlightingNode Highlighting helps to quickly visualize node connectivity - helping to quickly find and fix LVS problems.
Pad MapThis Pad IO cross-reference extractor tool generates bonding reports and creates bonding diagrams for packaging.  It also facilitates design data exchange from L-Edit to Altium PCB solutions.
Schematic Driven LayoutSchematic Driven Layout (SDL) encourages good design practices by keeping close synchronization between the schematic and the layout. Names of devices, cells and nets will be automatically set. Drawn routing is automatically labeled with the net name for easy inspection and management.SDL increases productivity and eliminates errors with automatic instancing of cells and parameterized devices. If device parameters change later, parameterized cells will be automatically updated.
Device Generator - StandardTanner's Standard Device Generator offers designers the ability to create basic cell constructs to improve productivity and quality of design.
SDL RouterSDL Router is an automatic routing engine integrated directly into SDL. It speeds layout by automatically routing non-critical nets while allowing the designer to manually route performance sensitive nets and parts of nets. It natively uses the routing geometry created by the user, and runs on all or a specified subset of nodes on each pass. SDL integration means users can easily highlight and rip up nodes, manage the manual and automatic routing status, and implement ECOs
HiPer DevGenTanner's High Performance Device Generator accelerates analog layout by generating several core design elements including current mirrors, differential pairs, resistor dividers and MOSFETs.
HiPer       L-Edit   Router
 
HiPer     L-Edit DevGen*
 
L-Edit IC
 
 
L-Edit Base
 
 
 
 
 
 
 

Verification

 included in package  Optional Add On

Product / Package
DRC-StandardTanner EDA's standard Design Rule Checking (DRC) offers designers an automated tool for verifying the correctness of a mask set.
Extract-StandardStandard Extract generates a flat SPICE netlist from layout for LVS or post-layout simulation
LVS-StandardStandard LVS accurately and efficiently compares two SPICE netlists to determine whether they contain equivalent circuit descriptions including merging of devices and matching of device parameter values.
HiPer Verify (DRC & Extract)Tanner EDA's HiPer Verify™ is a comprehensive yet affordable solution for analog/mixed signal IC design rule checking (DRC) and layout versus schematic checking (LVS). The tool uses advanced hierarchical algorithmic techniques to provide optimal performance for your designs and can meet the most challenging submicron verification requirements.
HiPer PX - 2DHiPer PX facilitates accurate modling of interconnect parasitic effects.  2D (fast) extraction pre-computes a table of values using the same methods as the 3D version, and then uses that table to estimate the parasitics based on a 2D representation of the layout. 2D can be run hierarchically or flat
HiPer PX - 3DHiPer PX facilitates accurate modling of interconnect parasitic effects. 3D (accurate) extraction creates a full 3D model of the layout and extracts parasitics based on finite element analysis using the vertical spacing, thickness, and dielectric constant of the layers. 3D extraction can only be run in flat mode.
HiPer Verify

MEMS

 included in package  Optional Add On

Product / Package
L-Edit: Layout EditorTanner EDA's L-Edit Pro combines the fastest rendering available with powerful features that exceed the needs of the most demanding user. This leading analog/mixed signal IC design tool enables you to get started with minimal training. You can draw and edit quickly, with fewer keystrokes and mouse clicks than other layout tools.
DRC-StandardTanner EDA's standard Design Rule Checking (DRC) offers designers an automated tool for verifying the correctness of a mask set.
DXF Import/ExportDXF Import/Export facilitates file sharing and tool interoperability for improved productivity.
Curve ToolsTanner EDA's curve tools add-in is a chamfers and fillets generator for all-angle objects.
SoftMEMS 3D Solid ModelerThe SoftMEMS 3D Solid Modeler is integrated with Tanner's L-Edit MEMS and L-Edit MEMS Designer packages. It creates a 3D view of a MEMS device from a selected layout area and fabrication process description.
L-Edit MEMS Design
L-Edit MEMS
 

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