From the President: Driving Analog Innovation in Partnership with Our Customers

One of the things we are very proud of at Tanner EDA is our long-term working relationships with our customers.  As evidenced in this issue's Analog Insights section in which we present our recent IEEE article collaboration with our customer and technical advisor Lewyn Consulting Inc. (LCI) and the Q&A in this quarter's Technical Advisor Spotlight with Lanny Lewyn, President of LCI, the view of our customers as partners is a part of our history, present, and future.

Tanner EDA has grown to where it is today organically since the launch of its first version of L-Edit-the company's analog layout tool-in 1988.  As a result, we have been able to work closely with customers on their design issues and challenges along the way to develop an EDA toolset, one that goes much beyond just layout, specifically for real-world designs and innovation being attempted by actual engineers and designers on the cutting edge.

The most recent capabilities developed in L-Edit for nanoscale analog CMOS design productivity are the direct result of cooperation with LCI. This teamwork helped us in product management and development at Tanner EDA to understand how best to enhance the tool into the next version and address current issues in analog design in a way that is most relevant to users. The prototype L-Edit utility is now used by LCI to tackle some of their latest design projects.

Our relationship with LCI is just one example of how we have our pulse on the EDA industry and more specifically our user base, its technical requirements and design needs, and are working closely with our customer partners to be more than just a vendor by driving analog innovation together.

- Greg Lebsack, President

What's New in Tanner Tools

Tanner's full-flow suite is now better than ever with the release of v15.11 of our tools. See for yourself how Tanner EDA is driving analog innovation.

S-Edit Additions

Enhanced Connectivity views can be viewed and edited in SPICE format

  • Spice, EDIF, and Verilog import now create Spice views
  • Spice views are saved with the design and the imported Spice is saved
  • Importing a hierarchical netlist creates separate cells for each subcircuit in the netlist

Enhanced access control of designs allow better team collaboration

  • Improved control over write permissions. When opening a design, users choose to open the design with Exclusive or Non-Exclusive access
    • Opening a design with Exclusive Access means reserving the right to save a design and no-one else can write to it while the exclusive user has it open
    • Opening a design with Non-Exclusive Access means there is the possibility of writing to the design in the future, as long as no one else secures a write reservation before the attempt to save

Corner Simulation Setup to easily simulate across process corners, temperatures, etc.

  • Corner Simulations can now be setup in the S-Edit Setup Spice Simulation dialog
  • Parameters, Temperature, and libraries may be set to any value for each corner that is defined
  • Shows corner set up dialog filled in for library corners

T-Spice Performance Improvements

  • 20% improvement in Transient Simulation Performance (DC Convergence) due to new compiler and solver
  • Update of Verilog-A, SimKit, and BSIM4 SOI models

W-Edit Enhancements

Histograms

  • New Histogram chart type
  • Results of .MEASURE commands in a Monte Carlo simulation are automatically plotted on a histogram upon completion of the simulation

Eye Diagrams

  • New eye diagrams chart type

Performance Improvements

Visit our product pages to learn more about Tanner tools for waveform analysis

L-Edit Productivity Gains

Wire drawing productivity enhancements greatly improve routing productivity

  • Manual routing is much faster with improved via placement tools - end a wire, place a contact, and start a new wire, all with one key stroke.

Object snapping to intersections

  • Snapping to intersections operates on all objects (boxes, polygons, wires, circles) and works through hierarchy

HiPer DevGen Additions

Resistor Dividers

  • Resistor generator has the ability to create resistor arrays

HiPer DevGen cells now work better with SDL Router

  • SDL is able to recognize resistors in a netlist that have the same L and W and combine them into a single resistor array.

Visit our product pages to learn more about Tanner tools for layout acceleration

HiPer Verify Enhancements

  • Major performance improvements for rules using Extent
  • Support for Size - Bevel option

Learn more about what's new in v15.11

Analog Insights: Is a New Paradigm for Nanoscale Analog CMOS Design Needed?

Lanny Lewyn, Lewyn Consulting and Nicolas Williams, Tanner EDA in Proceedings of the IEEE, Vol. 99, No. 1, January 2011

Abstract

In order to increase deep nanoscale analog CMOS design productivity, manufacturing yields, and also reduce time-to-market, Lanny Lewyn (Lewyn Consulting Inc. (LCI)) and Nicolas Williams (Tanner EDA) propose a new paradigm for circuit and physical design in the January 2011 Proceedings of the IEEE. The new paradigm includes using a set of restrictive physical design rules based on dimensionless GAMMA layout units, and also a dimensionless schematic notation. The schematic notation is used in combination with a technology-specific file to enable rapid circuit simulation in a multitude of nanoscale technology nodes and platform options. LCI is using the combination to design a low-power 12b 1GSPS single-leaf ADC that can be easily ported to the 40-28-22 nm high performance (HP) or low power (LP) platforms. To support the new circuit and physical layout paradigm it is necessary to utilize an EDA tool such as L-Edit Pro v. 15.10 that will convert the dimensionless GAMMA data base to the target technology scale while preserving the cell hierarchy. A set of algorithms is proposed which enables the layout tool to hierarchically shrink and export the GAMMA data to the GDSII data in microns. Existing tools that simply flatten and shrink the layout data create large file sizes. These sizes are much too large for time-efficient transport to the many tools used for nanoscale physical design verification. Tanner EDA has been a pioneer in the field of dimensionless physical design since its very first layout tools accommodated the LAMBDA-based dimensionless physical design approach proposed by Mead and Conway in the late 1970s.

Read the full article

FAE Focus: Sushmita Baswa

Sushmita Baswa is a Senior Applications Engineer at Tanner EDA's headquarters in Monrovia, California. She grew up in India and received her Bachelor's degree in Electrical Engineering. Sushmita later went on to complete her M.S. in Electrical Engineering with specialization in Analog Design at New Mexico State University. She joined Tanner EDA in 2005 and is currently the main support for both pre-sales and post-sales.

Sushmita enjoys Bollywood dancing, photography and spending time with her little girl.

Tips & Tricks

From Sushmita Baswa, Senior Applications Engineer and this quarter's FAE Focus:

Tip #1: Layer Palette and Drawing Toolbar Shortcuts

Show/Hide Layers

Layers can be shown or hidden by right-clicking the layer and selecting Show > Show "layer name" or Hide > Hide "layer name". Alternately, just middle-mouse click on the layer name in the layer palette to toggle that layer's shown/hidden status.

To hide all layers except one, right-click on the layer and select Hide > Hide all but "layer name". Alternately, hold down the F key and click on the layer name to hide all but the selected layer. If you hold down the F key and click again with the MMB the layers will toggle back on to all be shown. When the mouse is over the layer palette, the mouse button toolbar will reflect the middle-mouse button operations.

Show/Hide Objects

Just as described above for layers, objects can also be shown or hidden using the same techniques.

An object type (such as boxes, orthogonal wires, circles, Etc.) can be shown or hidden by right-clicking the object type on the drawing toolbar and selecting Show. The check mark will indicate if the object type is currently shown or hidden. Alternately, just middle-mouse click on the object type icon on the drawing toolbar to toggle that object's shown/hidden status.

To hide all object types except one, right-click on the object icon and select Hide All.

Alternately, hold down the F key and click on the object icon to hide all but the selected object type. If you hold down the F key and click again with the MMB the objects will toggle back on to all be shown. When the mouse is over the drawing toolbar, the mouse button toolbar will reflect the middle-mouse button operations.

Selecting Multiple Layers

To select multiple layers at one time, select the first layer and then use the G or F keys in conjunction with a mouse click to add multiple layers to the selection.

G + Left-Mouse Button (LMB) adds layers in sequence in the layer list.

F + Left-Mouse Button (LMB) adds layers which are not necessarily in sequence in the layer list.

Once multiple layers are selected, right-click on any of the selected layers and select Show > Show selected or Hide > Hide selected to show/hide the selected layers.

Tip #2: Creating a Compiled T-Cell

A compiled T-Cell can be created to protect the T-Cell code from being modified or viewed by users of the design file (.TDB) in which it is contained. First create the T-Cell and verify it is working and then perform the following steps to compile the T-Cell code and attach the created DLL to the T-Cell:

1. Go to File > New and select File type: UPI Macro. L-Edit will generate a macro template for you.

2. Copy the main function block of the T-Cell code from your working T-Cell and paste it into the macro template created in Step 1.

3. Save the macro file as a .cpp file (E.g., in this case: BoxGen.cpp).

4. Select Tools > Save As Dll to compile the macro.

5. Open up your T-Cell, delete the code from the T-Cell, and replace it with the following:

Binary: <name of the .dll file>
Macro: <name of the function call in the .dll>

Please note:  The .dll file must be located in the same directory as the .tdb file for the T-Cell to run the dll.

In This Issue

From the President: Driving Analog Innovation in Partnership with Our Customers

What's New in Tanner Tools: v15.11

Analog Insights: Is a New Paradigm for Nanoscale Analog CMOS

FAE Focus: Sushmita Baswa

Tips & Tricks

Technical Advisor Spotlight: Lewyn Consulting Inc.

Happenings @ Tanner

Happenings @ Tanner

Tanner EDA Press Releases Since the Last Issue:

Tanner EDA and TowerJazz Announce Qualified Process Design Kit and Reference Flow for 0.18um Power Management Process

Tanner EDA Expands Presence in Chinese Market

Read More on Our Press Page

Tanner EDA Participated in the Following Industry Events:

EDS Fair 2011
January 27 & 28 in Kanagawa, Japan

DesignCon 2011
January 31 - February 3

Tanner EDA presented "Breaking through the Analog IC Layout Design Bottleneck" and was a panelist in "PDKs for Analog IC Design-A Stakeholder Discussion"

Tanner EDA Will Be Participating in the Following Upcoming Industry Events:

Date 2011
March 14 - 18 in Grenoble, France

48th Annual Design Automation Conference (DAC) 2011
June 5 - 10 in San Diego, CA

Learn more about Tanner EDA events

Learn more about our Webinars

HiPer DevGen:
March 1 - 9:00-10:00 am PDT
April  21 - 2:00-3:00 pm PDT

HiPer Verify:
March 10 - 2:00-3:00 pm PDT
April 5 - 9:00-10:00 am PDT

L-Edit:
March 15  - 9:00-10:00 am PDT
April 14 - 2:00-3:00 pm PDT

Check out our Webinars homepage for more topics, dates, and times because we are always adding new sessions!

Sign up for training at Tanner in Monrovia, CA

Technical Advisor Spotlight: Lewyn Consulting Inc. (LCI)

Dr. Lanny Lewyn is president of Lewyn Consulting Inc. (LCI) in Laguna Beach, California and is a Life Senior Member of the IEEE. He holds 29 U.S. patents in CMOS and bipolar circuits, B.S. Eng. and M.S. E.E. degrees from the California Institute of Technology, and a Ph.D. E.E. from Stanford University.

Q: Please tell us about LCI and where you play in the analog IC design space.

A: LCI was founded 25 years ago to design and layout CMOS data conversion blocks and peripherals for telecomm and imaging applications.  Past customers include, Siliconix, SanDisk, PairGain, Solar Flare, ClariPhy, and Snowbush-Gennum.  The LCI 16b micropower-low-voltage x36 ADC array for an RSC-Teledyne ASIC currently processes all the imaging signals from the Hubble Advanced Camera for Survey's CCD sensors.  Recent work includes using a combination of circuit and physical design to mitigate reliability stress factors and overcome voltage limits inherent in deep nanoscale analog CMOS.  Our goal is to preserve high dynamic range while working at GHz conversions rates.

Q: What types of designs / applications are you working on and for customers in which industries?

A: The current project is an LCI-funded single-leaf 1GSPS 14b ADC that can be used in an x4 configuration with low skew and jitter clock distribution to extend conversion rates to 4 GSPS in 28nm.  It utilizes proprietary technology to operate at very low power levels for telecom and high-speed imaging applications.  Layout is being done with L-Edit Pro v15.10 in dimensionless units enabling porting to technologies from 180 to 22nm, and is intended for sale by LCI as IP.

Q: When did you first start using Tanner EDA tools and what has been the evolution of the relationship?

A: The first use of Tanner EDA tools was for Brooktree-Connexant where LCI developed portable design methodologies including dimensionless (F-unit) schematics and layout (GAMMA) rules.   The 14b LCI-Brooktree ADC was the first production ADC used by PairGain in the US and Alcatel in Europe for HDSL telecomm.  Later, LCI performed the layout of the Hubble ADC using L-Edit and subsequently assisted in the adoption of L-Edit as the layout standard for Snowbush-Gennum.  L-Edit was used at the Snowbush-Gennum Aguascalientes, Mexico design center to layout an LCI-designed 256x4MSPS ADC and an 8GBS SERDES-phy.  We have recently been serving as a technical advisor to Tanner and providing input on deep nanoscale physical design issues.   

Q: In the recent article you co-authored with Nicolas Williams in The Proceedings of the IEEE you propose a new paradigm for nanoscale.  How have you been able to use Tanner tools v15.10 to adopt this framework?

A: Because the first Tanner L-Edit tools were developed to use the Mead-Conway dimensionless LAMBDA units, it was the ideal tool for our GAMMA-based layouts.  A dimensionless layout approach based on restrictive physical design is now an essential strategy for increasing our nanoscale analog CMOS design productivity.  The use of GAMMMA allows us to reduce the number of required 1D+2D design rules at 28nm from well over 2,000 to less than 200.  However, in order to continue the use of the Tanner tools into the nanoscale regimes for very large layouts, the size of the data base transferred to the many required post-layout verification tools had to be reduced.  Biasing to final nm units usually requires flattening the data base so that cell-to-cell dimensions can be included.  At the 90nm technology node the long flattened-data transfer times to the verification tools caused excessive delays in the verification-debug cycle.  A prototype L-Edit utility developed by Nicolas Williams (Tanner EDA Director of Product Management) and his team is now used by LCI to generate the final nm-biased layers while preserving layout hierarchy.  The resulting GDSII stream file size reduction is more than an order of magnitude.


For further inquiries, contact Lanny Lewyn and Lewyn Consulting at lanny@pacbell.net.