From the President: Another Great Year
Thanks to innovative, cost-effective technology and excellence in customer support, we’ve just ended fiscal year 2011 (on May 31st) with solid growth. Revenue was up 8%, we added 139 new customers, and we’re continuing to reach out to technology partners for MEMS and for the analog and mixed-signal suite. As we continue to create powerful new tools and move as fast as standards allow towards more open systems, the dedication of our FAEs and the quality of both product development and ongoing maintenance and support have been major factors in our success. (For more information on our Fiscal year-end, click here).
Largely as a result of the release of HiPerSilicon v15 very early in fiscal year 2010, our existing loyal customers accounted for a 13% greater share of new purchases in 2011 than in 2010. Tanner EDA’s L-Edit MEMS and related product offerings also saw strong growth over the year; continuing to gain traction as this design space matures.
Product line growth was also significant. The company previewed version 16 of HiPer Silicon with OpenAccess database compatibility for layout (to be release in Q4 2011) at DAC 2011. The preview of v16 included Open Access database compatibility for layout, which enables designers to share files with colleagues and business partners using Si2 database standards. Larger design teams also appreciated the redesigned multi-user functionality. For more detail, see Tanner EDA at DAC in the sidebar. We also extended and deepened our PDK portfolio, announcing availability of a jointly-developed Tanner EDA/ Dongbu HiTek foundry-certified 0.18-micron analog CMOS PDF at the end of May.
2011 also saw Tanner EDA focusing on extending and deepening technology partner relationships in areas related to MEMs (SoftMEMs) and analog SPICE simulation (Berkeley Design Automation). See more.
One of the things that continues to make Tanner EDA successful is our close working relationships with all our users. Many thanks to customers old and new for continuing, with us, to drive analog design innovation.
- Greg Lebsack, President
Click here for a September 2011 interview of Greg Lebsack on SemiWiki.
What’s New in Tanner EDA Tools
V15 of our full-flow design suite got even better with releases v15.13 and v15.14.
In v15.13, we included major improvements to the Verilog export in S-Edit as well as modified temperature sweeps to give better user control. T-Spice saw an updated SPICE command wizard and a new duty cycle function that computes the duty cycle of a waveform. New legend controls were added to W-Edit along with a new linear regression measurement and expanded image format support. L-Edit saw improvements to the SDL placement algorithm and increased integration with our HiPer DevGen tool. HiPer Verify users saw improved performance and memory usage in Extract.
In v15.14, we made updates to Verilog views and improved conditions and other options for imports within S-Edit. T-Spice and W-Edit have several corrections and modifications to improve performance and user functionality. L-Edit received a host of functional corrections and several key improvements that dramatically improve quality of DXF imports. HiPer Verify has several functional improvements and performance enhancements.
For release notes, click here
V16, which will be release in Q4, was previewed at DAC 2011. Built on our 24-year legacy of providing industry-leading price-performance and interoperability, v16 will include full Open Access database compatibility for layout. By enabling file sharing based on Open Access database standards, large design teams will be able to more easily collaborate. For preview information, contact your sales person directly or email us at firstname.lastname@example.org
Analog Insights: Tanner EDA Partners with Berkeley Design Automation for Faster Spice Simulation
Tanner EDA and Berkeley Design Automation (BDA) are partnering to expand Tanner EDA’s powerful integrated circuit design environment to include a FastSPICE product. BDA’s Analog FastSPICE (AFS) is integrating with Tanner EDA’s S-Edit schematic capture and W-Edit waveform analyzer, giving analog designers unprecedented speed in a powerful, easy-to-use design system. Users will be able to drive the AFS simulator directly from S-Edit to get all of the speed and accuracy necessary for nanometer design. The faster simulations will allow users to perform a much more thorough verification of their designs.
BDA Analog FastSPICE
AFS accelerates the simulation through advanced numerical analysis and computational without sacrificing accuracy. AFS is different from most FastSPICE products because it generates true operating points and solves the full circuit matrix and original device equations for each timestep without ever taking shortcuts, thus ensuring the highest accuracy. AFS speed improvements are most dramatic when a design has digital circuitry or when simulating an entire design with parasitics. Faster simulations allow for more corner analyses or Monte Carlo runs, resulting in a much more thorough verification of a design. More comprehensive verification means a more robust design and less risk.
Tanner EDA users will have two choices for the simulation engine: T-Spice and AFS. AFS is good for entire designs with digital circuitry and/or parasitics while T-Spice is good for small blocks and circuits with high analog content. Users can create schematics of their design in S-Edit through its powerful, easy-to-use interface and then choose to simulate with either T-Spice or AFS. Users can then interactively view, measure, and analyze waveforms through W Edit’s intuitive and highly configurable multiple window, multiple chart interface. W-Edit will directly read both T-Spice and AFS results. After laying out a design in L-Edit, users can perform post-layout extraction with or without routing parasitics and then simulate them with either simulation engine. Tanner EDA shortens design cycles through tight integration of schematic, simulation, and waveform analysis. Users can easily select which simulator they want to use in the Setup Simulation Dialog.
The simulation of an 8-bit successive approximation ADC is shown as an example. The ADC has an 8-bit R2R DAC, a comparator, and various digital circuitry to control the DAC and produce the digital output. The design consists of 1,160 MOSFETs, 19 resistors, 1 capacitor, and 731 nodes.
The input of the ADC, the temperature, and five corner models were swept for a comprehensive verification. The input of the ADC was sweep over the range (0.0 to 2.2) with steps of ½ Least Significant Bit (LSB) (4.3mv). The temperature was swept from -55° to 125° in increments of 10°. The five major corner models were simulated (TT, FF, SS, FS, SF). Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) were measured at each temperature, input and corner.
|AFS||0.04 LSB||±1 LSB|
|T-Spice||0.04 LSB||±1 LSB|
For this ADC, AFS and T-Spice gave the same results although AFS produced results more quickly than T-Spice because the ADC had a large amount of digital circuitry. The results were easily displayed and analyzed in W-Edit regardless if they came from AFS or T-Spice. Below are plots of the DNL for all temperatures and corner models.
FAE Focus: Ragip Ispir, Tanner EDA Japan
Ragip Ispir is Technical Manager at Tanner EDA in Tokyo. He grew up in Turkey and received his Bachelor's Degree in Electrical and Electronics Engineering at Middle East Technical University (METU) in Ankara, Turkey. He later went on to complete his Ph.D., with specialization in RF and Microwave circuits, at Okayama University, Japan. Then he worked for Murata Manufacturing Co., Ltd. at Yokohama Technical Center as a design engineer for two years. Ragip joined Tanner EDA in 2006 and is currently responsible for technical support of both pre-sales and post-sales as well as PDK development.
Ragip enjoys hiking and reading books.
Tips & Tricks
From Ragip Ispir, Technical Manager at Tanner EDA in Tokyo
Tip #1: Making use of T-Cells from sample files
Many users are familiar with using T-Cells to generate parametric layouts. Like other cells, T-Cells can easily be copied -- even referenced -- from another file. In the sample folder, which can be setup by “Help > Setup Examples”, there are several examples of useful T-Cells. Below are some of them, with a short explanation and screen shot of the auto generated layouts.
|T-Cell Name||Auto Generated Cell|
|“Ellipse Generator”||an ellipse for which you can specify the number of sides (vertices).|
|“Rounded Rectangle”||a rectangle, corners of which can be rounded.|
|“Spiral Generator”||a spiral for which you can specify number, spacing, width of rings.|
|“Concentric Tori”||a number of tori for which you can specify start and stop angles, incremental spacing between each torus|
|“Layout TextGenerator”||Each letter a polygon. Basically generates cell operation similar to “Draw > Layout Generators > Layout Text Generator…”, but the text can be modified any time. The size of the text can be scaled by the Scale Factor in “Edit>Edit Properties|Instance”.|
|“NFET Generator”||a N-type MOSFET. Rules for the MOSFET are read in from Standard DRC rules setup. Before instancing this T-Cell, make sure that you have necessary layers and required rules defined in the DRC setup. In the T-Cell code, you can customize layer names or initialize parameters without referring to DRC rules setup.|
How to instance a T-Cell from another file
To instance a T-Cell distributed in the sample folder, simply run the “Cell > Instance” command. In the “Select Cell to Instance” dialog window, browse for the “Installed Sample Folder\Features By Tool\L-Edit\T-Cells”, select the tdb file, and then select the T-Cell from the list. In the “Reference type” select “Copy cell to current file”.
Note that, if you select “External reference”, a version of the cell (XRefCell) will still be copied to the current file, but it will be locked and linked to the original file so that if the original cell is changed you will be informed to update it when you open your file. You can examine XRef cells from “Cell > Examine XRefCells” and do operations like Redirect, Unlink etc.
If the technology names are different, a Conflict Resolution dialog is displayed. You need to put a check mark in “Ignore different technologies”. Also, if some layers are missing or a cell with the same name exists in your file, you need to take proper action as guided in the dialog.
When the T-Cell is copied to your design, you will be asked to enter parameters to generate the auto-generated cell.
Tip #2: Controlling the number of vertices when outputting GDSII file
In L-Edit, when you output to a GDSII file, curved objects like circles, arcs, tori and curved polygons are converted to polygons based on the manufacturing grid specified in the design. The manufacturing grid corresponds to the resolution at which the manufacturer can produce layout objects. If you have big curved objects in your design, such objects may exceed the maximum number of vertices the manufacturer can process. When exporting to GDSII, you can put a check mark in “Fracture polygons with more that 199 vertices”, where 199 is the maximum number of vertices which you can change. When exporting to GDSII, the curved objects will be first converted to polygons and then fractured if the number of vertices exceeds 199.
You can control the number of vertices of selected objects manually by the commands available in “Draw>Convert” menu.
Suppose that you have a circle with radius 500u, and the manufacturing grid in your design is set to 0.05u (“Setup > Design | Grid”). When you convert this circle to a polygon using the “Draw > Convert > To Polygon…” command, the resultant polygon will have 592 vertices. You can fracture it with the “Draw > Convert > Fracture Polygons…” command. If you set the maximum number of vertices to 199, you end up with 4 polygons each having 150 vertices.
In some cases, depending on the process, manufacturers charge more if the number of vertices exceeds a certain number. To decrease the number of vertices, you can increase the “Manufacturing grid” temporarily in “Setup > Design | Grid” before converting the selected curved objects to a polygon. If you change “Manufacturing Grid” from 0.05u to 0.5u, then convert the same circle to a polygon, you will find that it has only 179 vertices.
In This Issue
Happenings @ Tanner EDA
Tanner EDA Press Releases Since the Last Issue:
Tanner EDA in the News
Video interview of John Zuk at DAC
EETimes / Europe:
"Foundry-certified 0.18-micron analog CMOS PDK”
"High-productivity design tools for custom analog ICs”
Tanner EDA at DAC
DAC 2011 was held in San Diego from June 5-10. Tanner EDA and partners participated in exhibitor forums, a technical panel, and booth presentations and demonstrations. Tanner EDA also co-sponsored the 5th Annual IPL Luncheon at DAC: Interoperable PDK Standards are Here to Stay: New Era of Analog / Custom Innovation
Booth presentations by Tanner EDA & Partners:
A pre-release version of v16, including Open Access database compatibility for layout, which enables designers to share files with colleagues and business partners using Si2 database standards. Larger design teams also appreciated the redesigned multi-user functionality.
A joint solution developed by Berkeley Design Automation, Inc., the nanometer circuit verification leader, and Tanner EDA to accelerate circuit verification for A/MS designers. Both Tanner EDA and Berkeley Design Automation demonstrated the integration of Tanner EDA’s HiPer Silicon™ design suite with the Berkeley Design Automation Analog FastSPICE™ Platform.
Speaker: Ofer Tamir, Director CAD, Design Enablement & Support
Speaker: Joerg Doblaski, Senior Engineer
Tanner EDA on HiPer Verify High Performance Physical Verification
Speaker: Jeff Miller, Director of Product Management
Tanner EDA on HiPer DevGen Layout Acceleration
Speaker: Nicolas Williams, Director of Product Management
Analog IC Design: Why a Cohesive Tool Flow Drives Productivity
Mass Sivilotti, Chief Scientist, and John Zuk, VP Marketing & Strategy, outlined how productivity has become a mandate as analog IC designers strive to keep pace with the rapidly increasing market demands around quicker time-to-market. The productivity advantages of using a cohesive analog design tool suite comprised of schematic capture, simulation, layout, and physical verification were discussed. Preliminary responses from a recent survey of analog designers were presented (e.g., 28% of 42 preliminary respondents prefer to use development tools from a single vendor/ compatibility; expense and lack of single point of control were cited as main challenges when using tools from multiple vendors.)
To contribute to this survey of the effect of a cohesive workflow on A/MS design productivity, please visit the survey here. Full results will be published in Q4.
Analog IC Design at the Edge: A New Twist for Nanoscale Productivity
Dr Lanny Lewyn, President, Lewyn Consulting and Nicolas Williams, Director of Product Management for Tanner EDA, explained why nanoscale analog IC design productivity is a major concern as chip device counts approach 1 billion at 32 nm. A multitude of physical device pattern separation dimensions must now be entered into the pre-layout simulation models to accurately predict post-layout circuit performance. The presented approach -- based on the seminal work of Mead and Conway -- offers a novel method that enables rapid circuit simulation in a multitude of nanoscale technology nodes and platform options. As a result, pre-layout simulation accuracy is improved, which has a direct impact on increasing analog IC manufacturing yields while simultaneously increasing design productivity.
For a copy of this presentation, please contact email@example.com
Why the Delay in Analog PDK?
Mass Sivilotti from Tanner EDA, Tom Quan from Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) and Ofer Tamir from TowerJazz, with Steve Klass of 7Stalks Consulting acting as moderator, participated in a lively discussion on why it takes so long for foundries to release analog/ mixed-signal process design kits (PDKs). With the amount of A/MS content in designs growing, and the pressure to move to smaller process nodes increasing, the audience appreciated a chance to talk to the people who develop PDKs and reference flows.
Upcoming Industry Events
What's New in Tanner EDA Tools
View latest release notes here
Webinars on Demand
We are now offering Webinars On-Demand from our webinar library. Click to visit our Videos & Demos homepage to download webinars on:
- • Analog layout and Tanner EDA's L-Edit and Specialty Tools
- • Analog acceleration and Tanner EDA's HiPer DevGen tool
- • High performance physical verification and Tanner EDA‘s HiPer Verify
Training on Tanner EDA Tools
We offer training for analog and mixed-signal IC & MEMS design, taught by Tanner EDA experts with extensive design experience.
- • Training at Tanner EDA is available each month in our own classroom with workstations loaded with our entire tool suite. (See information below.)
- • Customized training can be planned and modified to meet the unique needs of an individual, design team or company.
- • All our training can be scheduled at your site, via the web or at our corporate offices in Monrovia, California.
Partner Spotlight: EDA Solutions
In November 2001, Tanner EDA appointed EDA Solutions as the exclusive European representative for Tanner EDA tools. Ten years on Paul Double, founder and CEO, joined us for a brief Q&A for this quarter’s issue of Tanner EDA Today:
Q: Please tell us a little about EDA Solutions.
A: We have been exclusive representatives for Tanner for 10 years now and in that time we have brought over 400% growth in sales in the region, and helped develop the tools, the brand and the reputation for Tanner as the best supported, most cost-effective design solution on the market.
Q: What makes Tanner EDA solutions a good fit for EDA Solutions to represent in Europe?
A: The design tools from Tanner EDA offer an effective and affordable alternative to those from the traditional big vendors. It therefore suits a small highly-focused company like ours to represent such a tool flow. Like Tanner EDA, we have a commitment to unrivalled customer service, which has helped us to build up a very mutually beneficial relationship with our customers.
Q: Which is the biggest market segment served by EDA Solutions? Is it commercial or educational? What design types?
A: We have a long-standing relationship with Europractice to serve our academic customers. For Tanner EDA in Europe, though, the majority of EDA Solutions’ focus has been on the commercial business. Our main application areas include sensing, imaging/display, power/HV and MEMS. We are helped in our role by the strength of the European analog/mixed signal foundries and our PDK support for their processes. Our traditional customer base has been startups, but we have seen a big surge in the number of more established design/product companies switching to Tanner EDA as more of the market becomes aware of the company’s “less is more” approach to providing just the right level of features and functionality within a complete analog design flow from schematic capture, circuit simulation, and waveform probing to physical layout and verification.