From the President: Is 2012 the Year for MEMS to Go Mainstream?
Did you know that more microelectrical mechanical systems (MEMS) designs have been taped out on Tanner EDA tools than on any other EDA software? Our sister division, Tanner Labs, launched our first MEMS product – L-Edit MEMS Design – in 1988 in response to a market need for cost-effective and easy-to-use EDA tools that would give engineers the performance and flexibility to handle complex design flows and help speed their design concept to silicon. Although L-Edit MEMS is now part of the Tanner EDA product line, Tanner Labs still maintains a low-volume MEMS foundry, providing us with firsthand feedback about tool usage and ways to help engineers improve productivity.
Our relationship with SoftMEMS goes back for many years as well. Mary Ann Maher, CEO of SoftMEMS, was a graduate student at Cal Tech with John Tanner (both studied under Carver Mead) and worked at Tanner Labs early in her career. Our ongoing collaboration with SoftMEMS allows designers to use best-in-class MEMS CAD tools from SoftMEMS coupled with standard analog and digital design tools from Tanner EDA for the co-design of MEMS devices, their associated electronics and packaging in commercial MEMS systems.
The MEMS market has grown steadily since 1988, and this important part of our heritage has grown along with it. Hundreds of customers -- including companies such as Hymite, Knowles Electronics, MEMSIC and SmartBead Technologies -- have discovered the value of the tightly-coupled affinity between L-Edit MEMS and their MEMS device designs. (See http://www.tannereda.com/customers/case-studies for usage case studies.) This March, French market research firm Yole Développement issued a report that projects another surge in demand as the sector industrializes a series of new devices. The MEMS market grew 17% in 2011, reaching $10.2 billion. Yole expects the market to pick up by the second half of 2012 and to enjoy a 14% compound annual growth rate (CAGR) through the next four years.
Check out the article on Tanner EDA and SoftMEMS: Eliminating Bottlenecks in MEMS-IC Co-Design to see how we are continuing to serve the MEMS community.
- Greg Lebsack, President
What's New in Tanner EDA Tools: v15.22
HiPer Silicon version 15.22 was released earlier this month. Details are available to existing customers on the Support Page at http://www.tannereda.com/support Highlights of this release include:
- T-Spice brings improved performance, expanded noise command options and support for HiSIM ver. 2.60.
- S-Edit sees expanded Verilog support, new built-in gates and improved parser functionality.
- HiPer DevGen, Tanner EDA's layout acceleration tool, gains a new feature for creating MOSFET arrays. This builds on the existing set of design primitives supported by the tool, continuing to boost productivity and quality.
Tanner EDA and SoftMEMS: Eliminating Bottlenecks in MEMS-IC Co-Design
Tanner EDA combines 24 years of industry experience in EDA tools and MEMS design and fabrication to provide MEMS design tools that are unparalleled in price-performance, functionality, and ease of use. See http://www.tannereda.com/mems for a comparison of Tanner EDA’s L-Edit MEMS Design and mechanical design tools. You also can read about how leading firms including Hymite, Knowles Electronics, MEMSIC, and SmartBed Technologies have used Tanner EDA’s L-Edit MEMS to effectively and efficiently design and manufacture innovative products.
In December 2011, Tanner EDA hosted a webinar to demonstrate L-Edit MEMS Design, which gives design engineers unsurpassed design rule checking (DRC) and a speedy design process. DRC before manufacturing provides savings on external foundry costs per run and internal labor costs while ensuring no delay in time to market. Automation speeds up the design process with enhanced Boolean operations, parameterized cell capabilities to automate changes, hierarchical structure and the ability to write macros in C to customize automation. Usability allows designers to start using the tool with almost no learning curve. Boolean operations ease mechanical reliefs and DRIE curved etch patterns while maintaining the actual design geometries on separate layers. Please click here for expanded coverage of this webinar.
Many of the delays in bringing MEMS-based systems to market stem from errors made in integrating the MEMS with the electronics, causing costly re-designs and missed market windows. Systems incorporating MEMS devices are growing in their level of integration and complexity, often including multiple MEMS sensors/actuators, analog and digital circuitry, micro-controllers, sensor fusion software and custom packaging. Working with SoftMEMS, we’ve co-designed tools for even more functionality, enabling designers to catch composition errors early and also to optimize the entire system, trading off requirements between the MEMS and electronics. The result is shortened time-to-market, higher product performance and lower manufacturing costs.
On April 10, 2012, Tanner EDA and SoftMEMS co-hosted a webinar that presented how MEMS CAD tools from SoftMEMS coupled with standard analog and digital design tools from Tanner EDA may be used for the co-design of MEMS devices, their associated electronics and packaging in commercial MEMS systems. Examples of important co-design issues include how to visualize MEMS devices in 3D from mask layout and fabrication step descriptions, how to co-simulate electronics and MEMS to calculate system timing, and how to model and evaluate the thermal, mechanical and electrical performance of new packaging concepts.
Highlights of the archived version of this webinar include:
- Create 3D models of devices from Tanner EDA’s L-Edit layout for virtual prototyping
- Create MEMS-specific layouts using SoftMEMS extensions to L-Edit
- Links to 3D FEM/BEM simulators – such as ANSYS, COMSOL, Oefelie
- Simulate MEMS/electronics using T-Spice with SPICE, Verilog-A and C-code
- Model of packaging effects on MEMS sensors
- MEMS-specific design rule checking
Visit http://tannereda.com/mems and follow the “Free Evaluation” link to qualify for a 30-day free evaluation copy of L-Edit MEMS.
FAE Focus: Rupinder Mand
Rupinder Mand is an Applications Engineer at Tanner EDA’s headquarters in Monrovia, California. He grew up in India, where he received his Bachelor’s degree in Electronics and Communications Engineering. He also holds an M.S. in Electrical Engineering from San Jose State University, with specialization in Analog and RF IC design. Rupinder, who joined Tanner EDA in 2011, provides pre-sales and post-sales technical support.
In his spare time, you can find Rupinder enjoying long drives or listening to music.
Tips & Tricks
From Rupinder Mand, Applications Engineer, Monrovia, CA.
Tip #1: Creating a TCL Script to Automate Simulation Settings
I would like to share a TCL script that will automatically set or update the simulation settings with just one click. Most customers know that S-Edit uses TCL scripting to execute operations. When an operation is initiated in S-Edit’s graphical interface, a corresponding TCL command is written to the Command Window. These commands can then be copied to a TCL script to automate the corresponding actions. You can either copy a single command or a bunch of commands that you want to execute.
In this example, I am going to show how to set up TCL script that will automatically define some of the General Simulation Settings. The first step is to perform the operations in S-Edit that you want to automate. Here I am defining some General simulation settings:
After clicking the “OK” button the corresponding TCL commands will be written to the Command Window as shown below.
Note that the corresponding TCL command will be outputted to Command Window for only those settings that are changed in S-Edit’s graphical interface; not all commands will be output. You can simply copy these commands from the Command Window to a text file and then define the TCL function like this.
Now, save this file with a ‘.tcl’ extension and give it a name. The ‘workspace userbutton’ command will add a button in the S-Edit toolbar with ‘MyTCLScript’ name when the script is loaded. You have to load this script by dragging and dropping it in the S-Edit Command Window. If you want to automatically load this script when S-Edit is started, place the script in this folder: C:\Users\
Simply clicking on this button will execute the TCL script. Similarly, you can automate other operations in S-Edit.
Tip #2: Scaling a Design in S-Edit
Sometimes there is a need to import EDIF files into S-Edit that are generated by third-party tools. When these EDIF files are imported into S-Edit, the symbols and schematics may have different sizes as compared to the existing design that you are working with. In this situation, the TCL command ‘design scale’ can be used to scale the schematic dimensions without affecting the device parameters. The great thing about the ‘design scale’ command is that it will scale all the elements including nets, ports and text. Below is the syntax for this command:
design scale –numerator [integer value] -denominator [integer value]
- design [designname]: name
- view [viewname]: name of view
- interface [interfacename]: name of interface
- page [pagename]: name of page (schematic view only)
- cell [cellname]: name of cell
- type layout | schematic | symbol | interface | chart | spice | veriloga: One of valid view types
This command can also be used on a single cell or on a specific view by utilizing the above mentioned optional arguments. For example, the following schematic can be scaled by using the ‘design scale’ command.
design scale -numerator 1 -denominator 2 -design RingVCO
The above command will only scale the cells in ‘RingVCO’ design by a factor of 0.5. The other libraries that are referenced in this design will not be affected. Below is the scaled schematic.
Tanner EDA User Community
by Sushmita Baswa
Thanks to all of you who are using the Tanner EDA User Community to connect with other designers and share tips on using the features in Tanner EDA tools. In just six months, the community has grown to over 600 active members who are learning new technologies and best practices; sharing information, ideas and successes (70 topics at last count); and even helping each other to find skilled designers or offer services. The Forum allows us to communicate with other experts day or night, getting and giving help as needed.
As the Community moderator, I am enjoying “listening” to you discuss your own issues openly with your peers around the world without getting into company or personal specifics. You are such a techie group! It’s inspiring how much we all learn from each other when we access the years of expertise and knowledge we share.
As you can tell on the forum, we value your input, too, for ongoing product development. Some interesting discussions on nano-scale design with Tanner EDA tools have included:
- Does analog CMOS layout methodology favor using automated layout methods when making the transition to deep nanoscale physical design?
- Is L-EDIT useful for deep-nanoscale analog CMOS designs?
- Does L-EDIT work well with the high data content typical of complex nanoscale analog CMOS designs?
- Does analog CMOS layout methodology have to change radically when making the transition to deep nanoscale physical design?
- Does L-EDIT work acceptably well with the very fine-grid resolutions typical of deep-nanoscale layout?
To join us in the User Community, register at http://www.tannereda.com/forum/index.php?mode=register&rb_v=ucp It’s free. We look forward to hearing from you.
In This Issue
Happenings @ Tanner EDA
Tanner EDA Press Releases Since the Last Issue:
Tanner EDA in the News
“AMS Design using Co-Simulation” by Daniel Payne on SemiWiki
“MEMS and IC Co-design” by Daniel Payne on SemiWiki
“Lines blurring between digital, analog design worlds” by Dylan McGrath in EETimes
“Panelists: Bridging the Gap Between Analog and Digital Design” by Richard Goering in Cadence Industry Insights
"Low-power IC design in Switzerland" on SemiWiki.com
“Electronics Surge” by Dennis Spaeth in MICROmanufacturing magazine
“Tanner and Dongbu HiTek release PDK for BCDMOS chips” by Brian Bailey in EETimes
“Choosing a design flow for mixed-signal asics” by Paul Double in ElectronicsWeekly.com
“AMS Design at AnSem” by Daniel Payne
Tanner EDA at DATE 2012
Jeff Miller, Director of Product Management, participated in a panel entitled “Analog Productivity – Design and Test of Analog/Mixed Signal ASICs” chaired by Prof. Georges Gielen, Head of Department of Electrical Engineering (ESAT), Katholieke Universiteit Leuven, Belgium.
Starting with the premise that analog is an ever-important aspect of emerging microelectronic applications, never has the need to improve productivity been more acute. Drawing from a range of industry experts, participants discussed the main areas affecting this field, namely analog/digital co-design, IP reuse, layout automation and design for test/yield. Jeff represented the point of view of system-level simulation Other panellists:
- • Ciaran Whyte, CTO, IC Mask Design Limited, Ireland / Layout acceleration
- • Dr. Holger Haberla, Non-Volatile Memory Design Manager, X-FAB Semiconductor Foundries AG, Germany / IP reuse
- • Marc Hutner, DFT Architecture Engineering, Teradyne, USA/ Design for test, yield
Tanner EDA also previewed HiPer Simulation A/MS, an integrated solution that gives designers a complete analog design flow from schematic capture, circuit simulation, and waveform probing to physical layout and verification, logic synthesis and mixed VHDL and Verilog simulation. HiPer Simulation A/MS will combine industry-leading technologies into a highly productive design flow for mixed-signal design with industry-leading price-performance.
Tanner EDA at DesignCon 2012
Jeff Miller, Director of Product Management, participated in a panel at DesignCon 2012 entitled “Is It Time for an Analog Comeback?” Moderated by Brian Bailey of EETimes, the panel discussed whether the movement of analog circuitry onto the chip has resulted in better design tools, whether analog content will increase or be more problematical as geometries shrink, and what some current and future issues will be. Jeff summarized the deep submicron challenges that often cause analog design to be a bottleneck to the total design timeline. Other panellists:
- • Warren Savage, CEO, IPextreme
- • Mladen Nizic, Engineering Director for Mixed-signal Solutions, Cadence
- • Harold Joseph, Director for PSOC Analog Marketing, Cypress Semiconductor
- • Navaraj Nandra, Senior Director of Designware Marketing & Mixed-signal IP, Synopsys
Design & Elektronik Forum
Tanner EDA - Co-Sponsor: Ultra Low Power
Visit us at the Tanner EDA Booth
October 10, 2012 - Munich, Germany
1-2 May 2012 -- Tel Aviv, Israel. Booth in entrance foyer
DAC49: Design Automation Conference 2012
3-7 June 2012 – San Francisco, CA, USA. Booth #1126
Tanner EDA will be hosting live seminars demonstrating our latest A/MS tool flow that brings together Aldec, Incentia and Tanner EDA. Look for upcoming events in
Taiwan – May 2012
Japan – June 2012
Webinars on Demand and Product Demos
- • HiPer Silicon v15 Full-Flow Tool Suite
- • Watch: Eliminating Bottlenecks in MEMS-IC Co-design – Tanner EDA & SoftMEMS
- • HiPer DevGen Analog Layout Acceleration
- • L-Edit MEMS Design
Webinars On-Demand Library
- • Watch: Layout acceleration and HiPer DevGen
- • Watch: High performance physical verification and HiPer Verify for a best practices workflow
- • Watch: Analog layout productivity and L-Edit and Specialty Tools
Training on Tanner EDA Tools
We offer training for analog and mixed-signal IC & MEMS design, taught by Tanner EDA experts with extensive design experience.
- • Training at Tanner is available each month in our own classroom with workstations loaded with our entire tool suite. (See course schedule here.)
- • Customized training can be planned and modified to meet the unique needs of an individual, design team or company.
- • All our training can be scheduled at your site, via the web or at our corporate offices in Monrovia, California.
Partner Spotlight: IC Mask Design
IC Mask Design, based in Ireland, is a leading provider of physical design services, and IC layout training programs to the global semiconductor industry. Tanner EDA exclusively licenses IC Mask Design’s patented layout acceleration technology, which is integrated into Tanner EDA’s custom IC design suite. This collaboration, which began in 2007, offers engineers a platform to boost IC Layout productivity without compromising on quality. Fergal Brosnan, CEO of IC Mask Design, joined us for a brief Q&A for this quarter’s issue of Tanner EDA Today:
Q: Please tell us a little about IC Mask Design?
A: IC Mask Design was founded in 2002 to deliver physical design services in the areas of RF, mixed-signal and digital designs to a customer base across Europe and North America. We provide specific expertise in emerging technology nodes, with over 90% of our business focused on 65nm and below. We also provide a range of methodology-based IC layout training courses, with over 1000 engineers worldwide having attended our courses to date.
Q: What prompted the partnership with Tanner EDA?
A: IC Mask Design was using Tanner’s HiPer Silicon tool suite and had identified a pain point for designers within our own team. As a design services company, we were consistently looking at methods to reduce design cycle times, without compromising on quality. We recognized that there were certain common analog structures -- such as resistor dividers, current mirrors and differential pairs -- where automation of these structures would provide a significant acceleration in the overall design flow. We developed technology to accelerate the process for creating these structures and worked with Tanner EDA to embed this into their toolset. At all times we focused on producing high quality layout that was “silicon aware.”
Q: How is IC Masks’ technology integrated into Tanner EDA tools?
A: In 2010, Tanner EDA released a breakthrough add-in tool – HiPer DevGen -- based on IC Mask Design’s proprietary technology that accelerates physical design activities to improve productivity. The new tool embeds seamlessly into Tanner EDA’s powerful and robust layout editor. Designers are able to automatically generate devices and structures that are silicon-aware and are contextually tuned for their own specific layouts. This solution gives engineers and managers the benefits of quality and productivity by consistently applying analog layout knowledge and experience to eliminate errors and speed layout cycles.
Q: How has HiPer DevGen been received by the market?
A: We’ve had strong response from users – with adopters citing cycle time reductions from days to minutes. The types of designs are wide-ranging, with strong affinity in industry applications such as image sensors and life sciences.
Q: What does the roadmap look like for ongoing collaboration?
A: Along with customer interest has come customer requests for additional features. So we are currently working with a number of customers to identify key capabilities to add to upcoming software releases. We are excited at the prospect of our continued relationship.