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Analog Front End, HiPer Simulation | Tanner EDA

HiPer Simulation is Tanner EDA's design entry and simulation offering. This integrated front-end tool suite includes S-Edit for schematic capture, T-Spice for circuit simulation, and W-Edit for waveform viewing and analysis. Verilog-A is also included; providing the opportunity for even greater productivity through behavioral modeling.

HiPer Simulation AFS adds Berkeley Design Automation's Analog FastSPICE product into the tool suite. This high performance add-on provides foundry-certified nm SPICE accuracy at industry-leading speed and the ability to perform Transient Noise Analysis.


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HiPer Simulation AMS is for engineers and designers in need of a complete mixed-signal front end tool suite.  This package adds a Tanner edition of Aldec's Riviera-PRO as well as providing Verilog-AMS for co-simulation.  HiPer Simulation enables abstract top-down design; allowing Designers to start from the top level with abstract Verilog-A/D/AMS, fill in detailed block-level RTL, then gate and transistor level, and easily manage and simulate it.

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HiPer Simulation includes:

T-Spice: Analog Simulation

T-Spice is a complete design capture and simulation solution that provides accuracy and convergence with market-proven reliability. To transform your ideas into designs, you must be able to simulate large circuits quickly and with a high degree of accuracy. That means you need a simulation tool that offers fast run times, integrates with your other design tools, and is compatible with industry standards. To transform your ideas into designs, you must be able to simulate large circuits quickly and with a high degree of accuracy. That means you need a simulation tool that offers fast run times, integrates with your other design tools, and is compatible with industry standards.

  • T-Spice offers HSPICE® and PSpice® compatible syntax and supports the latest industry models, including PSP, BSIM3.3, BSIM4.6, BSIM SOI 4.0, EKV 2.6, MOS 9, PSP, RPI a-Si & Poly-Si TFT, VBIC, and MEXTRAM models to allow easy integration of legacy designs and foundry models.
  • T-Spice lets you precisely characterize circuit behavior using virtual data measurements, Monte Carlo analysis, and parameter sweeping.
  • For greater efficiency and productivity, T-Spice puts you in control over your simulation process with an easy-to-use graphical interface and a faster, more intuitive design environment.
  • With key features such as multi-threading support, automatic selection of advanced convergence algorithms, and “.alter” command for easy what-if simulations with netlist changes, T-Spice saves you time and money during the simulation phase of your design flow.
  • Additional T-Spice Engine licenses can boost your innovation and experimentation capability with greater simulation capacity.  Perform simultaneous runs and increase simulation run-time by adding up to ten (10) more engines.  Click here to contact our Sales Team regarding this capability.
  • T-Spice supports Verilog-A behavioral modeling. Click here to read the whitepaper on this important productivity aid

Arrow View the T-Spice Datasheet

S-Edit: Schematic Capture

Tightly integrated with Tanner EDA's T-Spice simulation, L-Edit layout editor, and HiPer verification tools, S-Edit gives you the power you need to handle your most complex full custom IC design capture. Its efficient design capture process integrates easily with third-party tools and legacy data. S-Edit enables you to explore design choices and provides an easy-to-use view into the consequences of those choices.

  • S-Edit's tight integration with SPICE simulation allows viewing operating point results directly on the schematic and performing waveform cross-probing to view node voltages and device terminal currents or charges.
  • S-Edit imports schematics via Open Access and via EDIF from third party tools, including Cadence, Mentor, Laker, ORCAD and ViewDraw with automatic conversion of schematics and properties for seamless integration of legacy data.
  • S-Edit's schematic design checks enables you to check your design for common errors such as undriven nets, unconnected pins and nets driven by multiple outputs so you can catch errors early before running simulations.

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Arrow View the S-Edit Datasheet

 

 

W-Edit: Waveform Viewing & Analysis

The W-Edit waveform analysis tool is a comprehensive viewer for displaying, comparing, and analyzing simulation results. W-Edit provides an intuitive multiple-window, multiple-chart interface for easy viewing of waveforms and data in highly configurable formats

  • W-Edit is dynamically linked to T-Spice and S-Edit with a run-time update feature that displays simulation results as they are being generated and allows waveform cross-probing directly in the schematic editor for faster design cycles.
  • Focus on and optimize your design with W-Edit's advanced features such as automatically calculating and displaying FFT results in a variety of formats, including dB or linear magnitude, wrapped or unwrapped phase, and real or imaginary parts.
  • W-Edit allows creation of new traces based on mathematical expressions of other traces for advanced analysis and easy comparison with measured data.

 

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    Read more about the latest enhancements to W-Edit

     

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