Tanner EDA Webinars
Analog Layout Productivity
With pressure to reduce time to market and with resources increasingly constrained, tools that can enable maximum productivity are mission-critical. Tanner EDAâ€™s L-Edit for physical layout is a powerful, robust layout editor that is so easy to use it requires virtually no learning curve to get started.
Come see it for yourself!
High Performance Physical Verification Tools for a Best Practices Workflow
It is no secret that a best practice workflow is to have iterative verification throughout the design cycle. The high price of â€œgold standardâ€ physical verification tools often forces designers to work with short-term licenses and postpone their verification phase to the very end of design and layout. This creates risk and uncertainty that can lead to errors in tape out and respins that ultimately delay time to market.
Learn how Tanner EDA's HiPer Verify works to promote--rather than distort--your natural physical layout workflow and mitigate risk and uncertainty while reinforcing an iterative verification methodology.
Analog Layout Acceleration Live Tool Demonstration
Tanner EDA would like to invite you to learn about a game-changing approach to accelerating analog IC layout and to introduce our newly released industry-leading tool for device generation. HiPer DevGen (High Performance Device Generator), integrates seamlessly with our renowned layout editor (L-Edit) and provides unparalleled productivity gains.
A Tanner EDA product manager will be driving the tool for a live demonstration. You will see first-hand how to reduce weeks of design time into minutes using HiPer DevGen for current mirrors, differential pairs, and/or resistor arrays in your analog designs.